CY7C1354C CYPRESS [Cypress Semiconductor], CY7C1354C Datasheet - Page 19

• Manufacturer Part Number: CY7C1354C
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05538 Rev. *G
Switching Characteristics
t
Clock
t
F
t
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes:
17. This part has a voltage regulator internally; t
18. Timing reference level is 1.5V when V
19. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
20. t
21. At any given voltage and temperature, t
22. This parameter is sampled and not 100% tested.
Power
CYC
CH
CL
EOV
CLZ
CO
EOV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
MAX
Parameter
initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
[17]
, t
CLZ
, t
EOLZ
, and t
V
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
OE LOW to Output Valid
Clock to Low-Z
Data Output Valid after CLK Rise
OE LOW to Output Valid
Data Output Hold after CLK Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
Address Set-up before CLK Rise
Data Input Set-up before CLK Rise
CEN Set-up before CLK Rise
WE, BW
ADV/LD Set-up before CLK Rise
Chip Select Set-up
Address Hold after CLK Rise
Data Input Hold after CLK Rise
CEN Hold after CLK Rise
WE , BW
ADV/LD Hold after CLK Rise
Chip Select Hold after CLK Rise
CC
EOHZ
(typical) to the First Access Read or Write
x
x
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
Set-up before CLK Rise
Hold after CLK Rise
[20, 21, 22]
[20, 21, 22]
[20, 21, 22]
DDQ
Description
EOHZ
Over the Operating Range
= 3.3V and is 1.25V when V
power
is less than t
is the time power needs to be supplied above V
[20, 21, 22]
[20, 21, 22]
EOLZ
and t
CHZ
DDQ
is less than t
[18, 19]
= 2.5V.
Min.
1.25
1.25
1.25
1.25
4.0
1.8
1.8
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
CLZ
–250
to eliminate bus contention between SRAMs when sharing the same
Max.
250
2.8
2.8
2.8
2.8
2.8
DD
minimum initially, before a Read or Write operation can be
Min.
2.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
5
0
–200
Max.
200
3.2
3.2
3.2
3.2
3.2
Min.
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
6
0
–166
CY7C1354C
CY7C1356C
Max.
166
3.5
3.5
3.5
3.5
3.5
Page 19 of 28
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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