CY7C1354A CYPRESS [Cypress Semiconductor], CY7C1354A Datasheet - Page 15

• Manufacturer Part Number: CY7C1354A
• Description: 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05161 Rev. *B
TAP Timing and Test Conditions
Identification Register Definitions
Scan Register Sizes
TEST MODE SELECT
Revision Number(31:28)
Device Depth (27:23)
Device Width (22:18)
Reserved (17:12)
Cypress Jedec ID Code (11:1)
ID Register Presence Indicator (0)
Instruction
Bypass
ID
Boundary Scan
Register Name
TEST DATA OUT
TDO
TEST DATA IN
TEST CLOCK
Instruction Field
Z
(TMS)
(TDO)
(TCK)
0
(TDI)
= 50
(a)
Bit Size (x36)
GND
1.5V
32
70
3
1
C
50
L
= 20 pF
t
THTH
00011100100
t
t
MVTH
DVTH
256K x 36
XXXXXX
Bit Size (x18)
00110
00100
XXXX
1
t
t
THMX
THDX
32
51
3
1
00011100100
512K x 18
XXXXXX
XXXX
00111
00011
1
t
TLQX
V
t
THTL
SS
t
TLQV
1.5 ns
Reserved for revision number.
Defines depth of 256K or 512K words.
Defines width of x36 or x18 bits.
Reserved for future use.
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
3.0V
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
ALL INPUT PULSES
1.5V
t
Description
TLTH
1.5 ns
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