CY7C1354A CYPRESS [Cypress Semiconductor], CY7C1354A Datasheet
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CY7C1354A
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CY7C1354A Summary of contents
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... Chip Enables (CE, CE Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc, and BWd), and Read-Write Control (WEN). BWc and BWd apply to CY7C1354A/GVT71256ZC36 only. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data occurs, either Read or Write ...
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... SA0, SA1, SA CEN A0, A1, A CLK OE# OE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information. Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 [1] Address Control Input Registers Control Logic Mux Output Registers Output Buffers ...
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... DQd 18 DQd 19 V CCQ DQd 22 DQd 23 DQd 24 DQd DDQ 27 DQd 28 DQd 29 DQd 30 Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 100-lead TQFP Packages NC DQb DQb 79 DQb CCQ CCQ DQb 75 DQb ...
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... Pin Configurations (continued) CY7C1354A/GVT71256ZC36 (256K × 36)–7 × 17 BGA CCQ DQc E DQc F V CCQ G DQc H DQc J V CCQ K DQd L DQd M V CCQ N DQd P DQd CCQ CY7C1356A/GVT71512ZC18 (512K × 18)–7 × 17 BGA CCQ ...
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... ADV/ Read or Write operation. The data bus activity for the current cycle takes place two clock cycles later. Input- Clock: This is the clock input to CY7C1354A/GVT71256ZC36. Except Synchronous for OE, ZZ and MODE, all timing references for the device are made with respect to the rising edge of CLK. ...
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... The effect of CEN sampled HIGH on the device outputs the LOW-to-HIGH clock transition did not occur. For normal operation, CEN must be sampled LOW at rising edge of clock. CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Pin Description or to GND. ...
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... CC Output IEEE 1149.1 Test Inputs: LVTTL-level output. If Serial Boundary Scan (JTAG) is not used, these pins can be floating (i.e., No Connect). Supply Power Supply: +3.3V –5% and +5%. Ground Ground: GND. CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Pin Description are used with used with CE and CE 2 has inverted polarity but otherwise is identical to ...
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... Linear Burst Address Table (MODE = V Fourth First Address Address [5] (internal) (external) A...A A... A...A A... A...A A... A...A A... CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Pin Description or to GND. CC [4] BWa BWb BWc ...
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... External L L Write Next External L L Write Next are all True. 3 HIGH means are HIGH CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Min. Max. – 0. – 0. CYC 2t CYC CE CEN BWx OE (2 cycles later ...
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... TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the LSB of any register (see Figure 2). Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Performing a TAP Reset The TAP circuitry does not have a reset pin (TRST, which is optional in the IEEE 1149.1 specification). A RESET can be ...
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... IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power-up and at any time the TAP controller is placed in the test-logic reset state ...
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... TMS at the rising edge of TCK. Document #: 38-05161 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE- EXIT2-IR 1 UPDATE- [21] Page ...
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... A OHC [23 8.0 mA OLT [23 8.0 mA OHT /2; undershoot: V (AC) <–0.5V for t < t KHKH IL KHKH must not exceed V . Control input signals (such as WEN and ADV/LD) may not have pulse widths less than CC CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 0 Selection Circuitry [22] Min. Max. 2 0.3 CC –0.3 0.8 – ...
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... CS CH 27. Test conditions are specified using the load in TAP AC test conditions. Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 [26, 27] Over the Operating Range Description Min. Max. Unit ...
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... XXXXXX XXXXXX 00011100100 00011100100 1 1 Bit Size (x18 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 ALL INPUT PULSES 3.0V 1.5V 1 TLTH Description Reserved for revision number. Defines depth of 256K or 512K words. Defines width of x36 or x18 bits. Reserved for future use. Allows unique identification of DEVICE vendor. ...
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... Do not use these instructions; they are reserved for future use. 110 Do not use these instructions; they are reserved for future use. 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations. CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Description Page ...
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... CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Signal Name TQFP Bump BWa 93 BWb 94 BWc 95 BWd 100 DQc 1 DQc 2 DQc 3 DQc 6 DQc 7 DQc ...
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... CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Signal Name TQFP Bump ID CLK BWa 93 BWb 100 DQb 8 DQb 9 DQb 12 DQb DQb 18 DQb ...
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... CC Device deselected; all inputs < > MAX CLK cycle time > t Min. KC < –2.0V for t < means no input lines are changing. CYC CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 [28] Ambient Temperature +70 C 3. +85 C Min. Max. 2 0.3 CC 2.0 1.7 –0.3 0.8 – ...
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... KQHZ KQLZ OEHZ CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Typ. Max 6.5 TQFP Typ ALL INPUT PULSES 90% 90% 10% 10% 1.0 ns (c) -6/ -7.5/ -10/ 133 MHz 100 MHz Max. Min. Max. Min. Max. 7 ...
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... Pipeline Read . Q(A ) represents the first output from the external address etc., where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the 2 is HIGH. 2 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 (Burst Wraps around (CKE# HIGH , eliminates to initial state) current L-H clock edge) Q(A +2) Q(A ...
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... Pipeline Write ) represents the first input to the external address etc., where address bits A0 and A1 are advancing for the four-word burst in the sequence defined by the state of 2 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 BW (CKE# HIGH , eliminates (Burst Wraps around current L-H clock edge) to initial state) ...
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... Document #: 38-05161 Rev BW KQHZ KQLZ KQX Q Read D Write Write . D(A ) represents the input data to the SRAM corresponding to address CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 Q(A ) Q(A 6 Read D Page ...
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... L-H clock transition did not occur. All internal registers in the SRAM will retain their previous states. Document #: 38-05161 Rev KQHZ Q KQLZ CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 KQX D Page Q ...
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... KQHZ Q KQX D(A ) represents the input data to the SRAM corresponding to address sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High-Z one 2 3 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 OEHZ Q D etc. 3 Page ...
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... I/Os Notes: 50.Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 51. I/Os are in three-state when exiting ZZ sleep mode Document #: 38-05161 Rev ZZS I (active DDZZ Three-state CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 t ZZREC Page ...
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... Ordering Information Speed (MHz) Ordering Code 200 CY7C1354A-200AC/ GVT71256ZC36-5 CY7C1354A-200BGC/ GVT71256ZC36B-5 166 CY7C1354A-166AC/ GVT71256ZC36-6 CY7C1354A-166BGC/ GVT71256ZC36B-6 133 CY7C1354A-133AC/ GVT71256ZC36-7.5 CY7C1354A-133BGC/ GVT71256ZC36B-7.5 100 CY7C1354A-100AC/ GVT71256ZC36-10 CY7C1354A-100BGC/ GVT71256ZC36B-10 200 CY7C1356A-200AC/ GVT71512ZC18-5 CY7C1356A-200BGC/ GVT71512ZC18B-5 166 CY7C1356A-166AC/ GVT71512ZC18-6 CY7C1356A-166BGC/ GVT71512ZC18B-6 133 CY7C1356A-133AC/ GVT71512ZC18-7.5 CY7C1356A-133BGC/ GVT71512ZC18B-7.5 100 ...
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... Ordering Information Speed (MHz) Ordering Code 166 CY7C1354A-166ACI/ GVT71256ZC36-6 CY7C1354A-166BGCI/ GVT71256ZC36B-6I 133 CY7C1354A-133ACI/ GVT71256ZC36-7.5I CY7C1354A-133BGCI/ GVT71256ZC36B-7.5I 100 CY7C1354A-100ACI/ GVT71256ZC36-10I CY7C1354A-100BGCI/ GVT71256ZC36B-10I 200 CY7C1356A-200ACI/ GVT71512ZC18-5I CY7C1356A-200BGCI/ GVT71512ZC18B-5I 166 CY7C1356A-166ACI/ GVT71512ZC18-6I CY7C1356A-166BGCI/ GVT71512ZC18B-6I 133 CY7C1356A-133ACI/ GVT71512ZC18-7.5I CY7C1356A-133BGCI/ GVT71512ZC18B-7.5I 100 CY7C1356A-100ACI GVT71512ZC18-10I CY7C1356A-100BGCI/ GVT71512ZC18B-10I Document #: 38-05161 Rev ...
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... Package Diagrams 100-lead Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05161 Rev. *B CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 51-85050-A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 119-Lead BGA ( ...
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... Document Title: CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Document Number: 38-05161 Issue REV. ECN No. Date ** 3000 4/21/00 *A 114095 03/12/02 *B 114095 05/30/02 Document #: 38-05161 Rev. *B Orig. of Change Description of Change CXV New Data Sheet GLC 1) Updated separate GLC 1) Added “I” temp 2) Added automatic power down to features ...