CY7C1354A CYPRESS [Cypress Semiconductor], CY7C1354A Datasheet - Page 14

• Manufacturer Part Number: CY7C1354A
• Description: 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05161 Rev. *B
TAP AC Switching Characteristics
t
f
t
t
Output Times
t
t
t
t
Set-up Times
t
t
t
t
t
t
Notes:
26. t
27. Test conditions are specified using the load in TAP AC test conditions.
THTH
TF
THTL
TLTH
TLQX
TLQV
DVTH
THDX
MVTH
TDIS
CS
THMX
TDIH
CH
Clock
Hold Times
Parameter
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
TCK LOW to TDO Unknown
TCK LOW to TDO Valid
TDI Valid to TCK HIGH
TCK HIGH to TDI Invalid
TMS Set-up
TDI Set-up
Capture Set-up
TMS Hold
TDI Hold
Capture Hold
Over the Operating Range
Description
[26, 27]
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Min.
20
8
8
0
5
5
5
5
5
5
5
5
Max.
50
10
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MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns