ICS8430-71B ICST [Integrated Circuit Systems], ICS8430-71B Datasheet - Page 11

• Manufacturer Part Number: ICS8430-71B
• Description: 700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
• Manufacturer: ICST [Integrated Circuit Systems]

The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
P
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If V
filter R7, C11, and C16 in between. Place this RC filter as close
to the V
C
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
8430BY -71
OWER AND
LOCK
CCA
shares the same power supply with V
CCA
T
RACES AND
as possible.
G
ROUNDING
Integrated
Circuit
Systems, Inc.
T
ERMINATION
PIN 1
U1
C14
C1
F
IGURE
C15
www.icst.com/products/hiperclocks.html
5B. PCB B
CC
PRELIMINARY
, insert the RC
LVCMOS-
TL1, TL21N are 50 Ohm
traces and equal length
OARD
C11
11
L
X1
TO
AYOUT FOR
700MH
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible.
Other termination schemes can also be used but are not
shown in this example.
C
The crystal X1 should be located as close as possible to the
pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length be-
tween the X1 and U1 should be kept to a minimum to avoid
unwanted parasitic inductance and capacitance. Other signal
traces should not be routed near the crystal traces.
R7
RYSTAL
TL1N
• The traces with 50Ω transmission lines TL1 and TL2
• Keep the clock trace on the same layer. Whenever pos-
• To prevent cross talk, avoid routing other signal traces in
• Make sure no other signal trace is routed between the
-3.3V LVPECL F
TL1
at FOUT and nFOUT should have equal delay and run
adjacent to each other. Avoid sharp angles on the clock
trace. Sharp angle turns cause the characteristic
impedance to change on the transmission lines.
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
clock trace pair.
C16
VCCA
C2
ICS8430B-71
Z
, L
R1
R3
Close to the input
pins of the
receiver
OW
J
ITTER
R2
R4
REQUENCY
GND
VCC
VIA
, C
ICS8430B-71
RYSTAL
REV. A SEPTEMBER 20, 2005
S
YNTHESIZER
I
NTERFACE
/