MT4LC1M16E5 MICRON [Micron Technology], MT4LC1M16E5 Datasheet - Page 10

• Manufacturer Part Number: MT4LC1M16E5
• Description: EDO DRAM
• Manufacturer: MICRON [Micron Technology]

NOTES
1. All voltages referenced to V
2. The minimum specifications are used only to
3. An initial pause of 100µs is required after power-
4. NC pins are assumed to be left floating and are
5. I
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. V
9. AC characteristics assume
10.V
11.In addition to meeting the transition rate
12.Measured with a load equivalent to two TTL gates
13.
14.Assumes that
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
indicate cycle time at which proper operation over
the full temperature range (0ºC
commercial) and (-20ºC
is ensured.
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
refresh requirement is exceeded.
not tested for leakage.
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
measuring timing of input signals. Transition
times are measured between V
between V
specification, all input signals must transit
between V
monotonic manner.
and 100pF; and V
t
operating parameters.
WRITE cycles.
READ-MODIFY-WRITE cycles. If
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit through-
out the entire cycle. If
t
t
MODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the
above conditions is met, the state of data-out is
indeterminate. OE# held HIGH and WE# taken
LOW after CAS# goes LOW results in a LATE
WRITE (OE#-controlled) cycle.
and
cycle.
WCS,
RWD
CWD
CC
IH
is dependent on output loading and cycle
(MIN) and V
t
AWD are not applicable in a LATE WRITE
t
RWD,
t
t
RWD (MIN),
CWD (MIN), the cycle is a READ-
IH
IL
and V
and V
t
t
AWD, and
RCD
t
RWD,
IL
OL
(MAX) are reference levels for
IH
IL
= 0.8V and V
).
(or between V
t
t
t
AWD
AWD and
RCD (MAX).
t
t
WCS <
WCS applies to EARLY
t
CWD are not restrictive
T
t
T = 2.5ns.
SS
A
DD
.
t
t
AWD (MIN) and
IH
WCS (MIN) and
80ºC for extended)
t
= +3.3V; f = 1 MHz.
WCS,
OH
t
t
and V
CWD apply to
WCS
T
IL
A
= 2V.
and V
t
70ºC for
RWD,
IL
t
(or
WCS
IH
) in a
t
REF
t
CWD
10
15.If CAS# is LOW at the falling edge of RAS#, Q will
16.These parameters are referenced to CAS# leading
17.If OE# is tied permanently LOW, LATE WRITE, or
18.LATE WRITE and READ-MODIFY-WRITE cycles
19.Assumes that
20.
21.The
22.The
23.Either
24.The first CAS#x edge to transition LOW.
25.Output parameter (DQx) is referenced to corre-
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
Additionally, WE# must be pulsed during CAS#
HIGH time in order to place I/O buffers in High-Z.
must have both
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. The DQs will provide the previously read
data if CAS# remains LOW and OE# is taken back
LOW after
OE# going back LOW, the DQs will remain open.
greater than the maximum recommended value
shown in this table,
amount that
t
achieves the open circuit condition and is not
referenced to V
rising edge of RAS# or CAS#, whichever occurs last.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
without the
must always be met.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
without the
be met.
cycle.
sponding CAS# input; DQ0-DQ7 by CASL# and
DQ8-DQ15 by CASH#.
OFF (MAX) defines the time at which the output
RAD was greater than the specified
RCD was greater than the specified
t
t
AA (
CAC (
t
t
RAD (MAX) limit is no longer specified.
RCD (MAX) limit is no longer specified.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCH or
t
RAC and
t
RAC [MIN] no longer applied). With or
t
OEH is met. If CAS# goes HIGH prior to
t
t
RAD (MAX) limit,
RCD limit,
t
RCD exceeds the value shown.
t
RCD <
OH
t
RRH must be satisfied for a READ
t
OD and
t
or V
CAC no longer applied). With or
t
16Mb: 1 MEG x16
RAC will increase by the
t
OL
RCD (MAX). If
t
. It is referenced from the
AA and
t
OEH met (OE# HIGH
t
CP.
t
AA,
EDO DRAM
t
CAC must always
t
RAC, and
©2001, Micron Technology, Inc
t
t
t
RAD (MAX)
RCD (MAX)
RCD is
t
t
RAD
RCD
t
CAC