MT48H16M16LF MICRON [Micron Technology], MT48H16M16LF Datasheet - Page 25

• Manufacturer Part Number: MT48H16M16LF
• Description: 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
• Manufacturer: MICRON [Micron Technology]

Figure 12:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
Consecutive READ Bursts
Note:
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL - 1.
Figure 7 on page 16 shows for CL of two and three; data element n + 3 is either the last of
a burst of four or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined
architecture. A READ command can be initiated on any clock cycle following a previous
READ command. Full-speed random read accesses can be performed to the same bank,
as shown in Figure 12 on page 25, or each subsequent READ may be performed to a
different bank.
COMMAND
COMMAND
ADDRESS
ADDRESS
Each READ command may be to either bank. DQM is LOW.
CLK
CLK
DQ
DQ
T0
T0
BANK,
COL n
BANK,
READ
COL n
READ
CL = 2
T1
T1
NOP
NOP
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
CL = 3
25
T2
T2
NOP
NOP
D
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
NOP
D
D
n + 1
OUT
OUT
n
T4
T4
BANK,
BANK,
READ
COL b
READ
COL b
X = 1 cycle
D
n + 2
D
n + 1
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
D
D
n + 2
n + 3
OUT
OUT
©2006 Micron Technology, Inc. All rights reserved.
T6
T6
NOP
NOP
D
n + 3
D
OUT
OUT
b
DON’T CARE
Operations
T7
NOP
D
OUT
b