MT46V64M4FJ-6 MICRON [Micron Technology], MT46V64M4FJ-6 Datasheet - Page 7

• Manufacturer Part Number: MT46V64M4FJ-6
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ T
Clock cycle time
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
ACTIVE to AUTOPRECHARGE command
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to V
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Data Hold Skew Factor
A
≤ 70°C; V
DD
Q = +2.5V ±0.2V, V
DD
CL = 2.5
CL = 2
DD
= +2.5V ±0.2V)
SYMBOL
t
t
t
CK (2.5)
t
t
DQSCK
t
t
t
t
t
t
WPRES
t
t
t
t
t
CK (2)
DQSH
DQSQ
t
WPRE
WPST
t
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
t
t
t
XSNR
XSRD
t
RPRE
RPST
REFC
MRD
t
WTR
t
t
t
t
QHS
REFI
t
t
t
DSH
t
t
t
t
IPW
RAP
RAS
RCD
RRD
VTD
t
DSS
t
t
RFC
t
WR
DH
QH
na
AC
CH
DS
HP
HZ
IH
IH
RC
CL
LZ
IS
IS
RP
F
S
F
S
7
t
-
CH,
-0.60
-0.70
MIN
0.45
0.45
0.45
0.45
1.75
0.35
0.75
0.75
0.80
0.80
0.25
t
0.35
0.75
t
-0.7
200
7.5
0.2
0.2
2.2
t
0.9
0.4
0.4
QH -
-6 (FBGA)
QHS
12
HP
18
42
60
72
18
18
12
15
75
6
0
1
0
t
CL
t
DQSQ
70,000
+0.60
+0.70
MAX
+0.7
0.55
0.55
0.35
1.25
0.50
70.3
1.1
0.6
0.6
7.8
DDR333 SDRAM Addendum
13
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
-
CH,
-0.60
-0.70
MIN
t
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.75
0.75
0.80
0.80
0.25
t
-0.7
t
200
7.5
0.2
0.2
2.2
0.9
0.4
0.4
QH -
12
QHS
18
42
60
72
18
18
12
15
75
-6T (TSOP)
HP
6
0
1
0
t
CL
t
DQSQ
70,000
+0.60
+0.70
MAX
+0.7
0.55
0.55
0.45
1.25
0.60
70.3
1.1
0.6
0.6
7.8
256Mb: x4, x8, x16
13
13
t
-
CH,
-0.75
-0.75
-0.75
MIN
0.45
0.45
0.50
0.50
1.75
0.35
0.35
0.75
0.90
0.90
0.25
t
200
t
7.5
7.5
0.2
0.2
2.2
0.9
0.4
0.4
t
QHS
15
20
40
65
75
20
20
15
15
75
HP
QH -
1
1
0
1
0
t
CL
-75Z
t
DQSQ
120,000
+0.75
+0.75
+0.75
MAX
0.55
0.55
0.50
1.25
0.75
70.3
PRELIMINARY
1.1
0.6
0.6
7.8
13
13
©2001, Micron Technology, Inc.
UNITS NOTES
t
t
t
t
t
t
t
t
t
t
t
t
t
ns
CK
CK
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
ns
CK
ns
CK
ns
µs
µs
ns
ns
CK
25, 26
25, 26
20, 21
45,52
45,52
26,31
26,31
18,42
18,43
25
30
30
31
34
14
14
14
14
46
35
50
42
19
23
23