MT46V64M4FJ-6 MICRON [Micron Technology], MT46V64M4FJ-6 Datasheet - Page 6

• Manufacturer Part Number: MT46V64M4FJ-6
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

GENERAL DESCRIPTION
namic random-access memory that operates at a fre-
quency of 167 MHz (
fer rate of 333Mb/s/p. DDR333 continues to use the
JEDEC standard SSTL_2 interface and the 2n-prefetch
architecture.
pertain to the DDR333 device and should be referenced
for a complete description of DDR SDRAM function-
CAPACITANCE (FBGA)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ T
CAPACITANCE (TSOP)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ T
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
PARAMETER
Delta Input/Output Capacitance:
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
PARAMETER
Delta Input/Output Capacitance:
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
The DDR333 SDRAM is a high-speed CMOS, dy-
The standard DDR200/DDR266 data sheets also
DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)
DQs, DQS, DM (for x4 or x8 devices)
DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)
DQs, DQS, DM (for x4 or x8 devices)
DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),
DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),
A
A
≤ 70°C; V
≤ 70°C; V
DD
DD
Q = +2.5V ±0.2V, V
t
Q = +2.5V ±0.2V, V
CK=6ns) with a peak data trans-
DD
DD
= +2.5V ±0.2V)
= +2.5V ±0.2V)
6
ality and operating modes. However, to meet the faster
DDR333 operating frequencies, some of the AC timing
parameters are slightly tighter. This addendum data
sheet will concentrate on the key differences required
to support the enhanced speeds.
a 60-ball FBGA package is utilized for DDR333. This
JEDEC-defined package promotes better package para-
sitic parameters and a smaller footprint.
In addition to the standard 66-pin TSOP package,
DDR333 SDRAM Addendum
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SYMBOL
SYMBOL
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
C
C
C
C
C
C
C
C
IO
IO
I
I
I
I
I
I
1
2
3
1
2
3
IO
IO
IO
I
I
IO
IO
IO
I
I
1
1
2
2
256Mb: x4, x8, x16
3.50
1.50
1.50
1.50
MIN
MIN
4.0
2.0
2.0
2.0
–
–
–
–
–
–
–
–
–
–
MAX
MAX
0.50
0.50
0.50
0.50
0.25
4.00
2.50
2.50
2.50
0.50
0.50
0.50
0.50
0.25
5.0
3.0
3.0
3.0
PRELIMINARY
©2001, Micron Technology, Inc.
UNITS
UNITS
p F
p F
p F
pF
pF
pF
pF
pF
pF
p F
pF
pF
pF
pF
pF
pF
pF
pF
13, 24
13, 29
13, 29
13, 24
13, 24
13, 24
13, 29
13, 29
NOTES
NOTES
13, 24
13, 29
13
13
13
13
13
13
13
13