MT46V64M4FJ-6 MICRON [Micron Technology], MT46V64M4FJ-6 Datasheet - Page 2

• Manufacturer Part Number: MT46V64M4FJ-6
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

FBGA 60-BALL PACKAGE DIMENSION
FBGA PACKAGE MARKING
Due to the physical size of the FBGA package, the full
ordering part number is not printed on the package.
Instead the following package code is utilized.
Top mark contains five fields
• Field 1 (Product Family)
• Field 2 (Product Type)
• Field 3 (Width)
• Field 4 (Density / Size)
• Filed 5 (Speed Grade)
Example top mark for a MT46V32M4FJ-6: DLBFJ
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS Ø 0.40
2.5 Volt, DDR SDRAM, 60-ball
SEATING PLANE
DRAM
DRAM - ES
x4 devices
x8 devices
x16 devices
256Mb
-6
-75Z
-75
-8
11.00
61X
0.10 C
5.50 ±0.05
0.45
BALL A9
0.850 ±0.075
C
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: Ø .33mm
4.50 ±0.05
Bottom View
9 .00 ±0.10
1.80
CTR
6.40
C L
3.20 ±0.05
C L
BALL A1
0.80 TYP
PIN A1 ID
1.00
TYP
8.00 ±0.05
16.00 ±0.10
SUBSTRATE: PLASTIC LAMINATE
12345
D
Z
L
B
C
D
H
J
P
F
C
MOLD COMPOUND: EPOXY NOVOLAC
1.20 MAX
2
FBGA PACKAGE PINOUT
M
M
A
D
G
H
M
A
B
C
D
E
G
H
K
B
C
E
F
K
L
A
B
C
D
G
H
K
F
J
L
J
E
F
J
L
DQ14
DQ12
DQ10
V
V
V
V
DQ8
V
V
NC
NC
NC
NC
NC
NC
NC
NC
SS
SS
SS
REF
REF
REF
1
1
1
DDR333 SDRAM Addendum
Q
Q
Q
Micron Technology, Inc., reserves the right to change products or specifications without notice.
V
V
DQ15
V
V
V
V
V
V
V
V
V
V
DQ7
A12
A11
A12
A11
A12
A11
V
NC
CK
A8
A6
A4
V
V
DD
DD
CK
A8
A6
A4
CK
A8
A6
A4
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
2
2
2
SS
SS
SS
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
UDQS
DQ13
DQ11
UDM
DQ3
DQ2
DQS
CK#
CKE
DQ6
DQ5
DQ4
DQS
DQ9
CK#
CKE
CK#
CKE
DM
DM
V
NC
V
V
V
V
V
A9
A7
A5
A9
A7
A5
A9
A7
A5
3
SS
SS
3
SS
SS
3
SS
SS
x16 (Top View)
x4 (Top View)
x8 (Top View)
256Mb: x4, x8, x16
4
4
4
5
5
5
6
6
6
M
M
M
A
B
C
D
G
H
K
A
B
C
D
E
G
H
K
A
B
C
D
G
H
K
E
F
J
L
F
J
L
E
F
J
L
LDQS
RAS#
RAS#
RAS#
WE#
LDM
WE#
WE#
DQ1
DQ2
DQ3
DQ2
DQ4
DQ6
DQ0
DQ1
BA1
BA1
BA1
V
V
V
V
V
V
NC
NC
NC
NC
NC
A0
A2
A0
A2
A0
A2
7
DD
DD
7
DD
DD
PRELIMINARY
DD
DD
7
©2001, Micron Technology, Inc.
V
V
V
V
V
V
CAS#
CAS#
CAS#
V
V
V
V
V
V
DQ0
DQ0
BA0
A10
BA0
A10
BA0
A10
V
CS#
V
CS#
V
CS#
A1
A3
A1
A3
NC
A1
A3
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
8
8
8
DD
DD
DD
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
V
V
V
DQ1
DQ3
DQ5
DQ7
A13
A13
A13
NC
NC
NC
NC
NC
NC
NC
NC
DD
DD
DD
9
9
9
Q
Q
Q