S908AC4MDRE FREESCALE [Freescale Semiconductor, Inc], S908AC4MDRE Datasheet - Page 60
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S908AC4MDRE
Manufacturer Part Number
S908AC4MDRE
Description
M68HC08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.S908AC4MDRE.pdf
(274 pages)
- Current page: 60 of 274
- Download datasheet (4Mb)
Configuration Registers (CONFIG1 and CONFIG2)
IRQPUD — IRQ Pin Pullup Control Bit
IRQEN — IRQ Pin Function Selection Bit
TIM2POS — TIM2 Position Bit
ESCIBDSRC — ESCI Baud Rate Clock Source Bit
OSCENINSTOP— Oscillator Enable in Stop Mode Bit
RSTEN — RST Pin Function Selection
COPRS — COP Reset Period Selection Bit
60
TIM2POS is used to reposition the timer channels for TIM2 to a different pair of pins. This allows the
user to free up one of the communication ports based on application needs.
ESCIBDSRC controls the clock source used for the ESCI. The setting of the bit affects the frequency
at which the ESCI operates.
OSCENINSTOP, when set, will allow the clock source to continue to generate clocks in stop mode.
This function can be used to keep the periodic wakeup running while the rest of the microcontroller
stops. When clear, the clock source is disabled when the microcontroller enters stop mode.
1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ pin and V
1 = Interrupt request function active in pin
0 = Interrupt request function inactive in pin
1 = TIM2 timer channel pins share PTB4 and PTB5
0 = TIM2 timer channel pins share PTB1 and PTB2
1 = Internal data bus clock used as clock source for ESCI
0 = BUSCLKX4 used as clock source for ESCI
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
1 = Reset function active in pin
0 = Reset function inactive in pin
1 = COP reset short cycle = 8176 × BUSCLKX4
0 = COP reset long cycle = 262,128 × BUSCLKX4
Reset:
Read:
Write:
The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will
leave this bit unaffected.
POR:
U = Unaffected
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
COPRS
Bit 7
0
0
Figure 4-2. Configuration Register 1 (CONFIG1)
LVISTOP
6
0
0
LVIRSTD
5
0
0
LVIPWRD
NOTE
4
0
0
LVITRIP
U
3
0
DD
SSREC
2
0
0
STOP
1
0
0
Freescale Semiconductor
COPD
Bit 0
0
0
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