S908AC4MDRE FREESCALE [Freescale Semiconductor, Inc], S908AC4MDRE Datasheet - Page 116
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S908AC4MDRE
Manufacturer Part Number
S908AC4MDRE
Description
M68HC08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.S908AC4MDRE.pdf
(274 pages)
- Current page: 116 of 274
- Download datasheet (4Mb)
Input/Output Ports (PORTS)
11.6.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRDx, be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRDx bit is configured as output.
PTDPUE[7:0] — Port D Input Pullup Enable Bits
116
Table 11-4
1. X = don’t care
2. I/O pin pulled to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
PTDPUE
These read/write bits are software programmable to enable pullup devices on port D pins
Bit
X
1
0
1 = Corresponding port D pin configured to have internal pull if its DDRD bit is set to 0
0 = Pullup device is disconnected on the corresponding port D pin regardless of the state of its
DDRD bit.
summarizes the operation of the port D pins.
DDRD
Reset:
Read:
Write:
Bit
0
0
1
DD
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
Figure 11-16. Port D Input Pullup Enable Register (PTDPUE)
by internal pullup.
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Bit 7
PTD
X
0
Bit
X
X
(1)
Input, Hi-Z
Input, V
6
0
Table 11-4. Port D Pin Functions
I/O Pin
Output
Mode
DD
(2)
(4)
5
0
Accesses to DDRD
4
0
DDRD7–DDRD0
DDRD7–DDRD0
DDRD7–DDRD0
Read/Write
3
0
2
0
PTD7–PTD0
Read
Pin
Pin
1
0
Accesses to PTD
Freescale Semiconductor
Bit 0
0
PTD7–PTD0
PTD7–PTD0
PTD7–PTD0
Write
(3)
(3)
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