S908AC4MDRE FREESCALE [Freescale Semiconductor, Inc], S908AC4MDRE Datasheet - Page 126
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S908AC4MDRE
Manufacturer Part Number
S908AC4MDRE
Description
M68HC08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.S908AC4MDRE.pdf
(274 pages)
- Current page: 126 of 274
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Enhanced Serial Communications Interface (ESCI) Module
13.3.1 Data Format
The SCI uses the standard mark/space non-return-to-zero (NRZ) format illustrated in
13.3.2 Transmitter
Figure 13-4
13.3.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control
register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control
register 3 (SCC3) is the ninth bit (bit 8).
13.3.2.2 Character Transmission
During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin. The ESCI
data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
To initiate an ESCI transmission:
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit
shift register. A 0 start bit automatically goes into the least significant bit (LSB) position of the transmit
shift register. A 1 stop bit goes into the most significant bit (MSB) position.
The ESCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the ESCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, high.
If at any time software clears the ENSCI bit in ESCI control register 1 (SCC1), the transmitter and receiver
relinquish control of the port pins.
126
1. Enable the ESCI by writing a 1 to the enable ESCI bit (ENSCI) in ESCI control register 1 (SCC1).
2. Enable the transmitter by writing a 1 to the transmitter enable bit (TE) in ESCI control register 2
3. Clear the ESCI transmitter empty bit (SCTE) by first reading ESCI status register 1 (SCS1) and
4. Repeat step 3 for each subsequent transmission.
(SCC2).
then writing to the SCDR. For 9-bit data, also write the T8 bit in SCC3.
shows the structure of the SCI transmitter.
START
START
BIT
BIT
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
BIT 0
BIT 0
BIT 1
BIT 1
BIT 2
BIT 2
Figure 13-3. SCI Data Formats
BIT 3
BIT 3
(BIT M IN SCC1 CLEAR)
9-BIT DATA FORMAT
(BIT M IN SCC1 SET)
8-BIT DATA FORMAT
BIT 4
BIT 4
BIT 5
BIT 5
BIT 6
BIT 6
OR DATA
PARITY
BIT 7
BIT 7
BIT
OR DATA
PARITY
STOP
BIT 8
BIT
BIT
START
NEXT
STOP
BIT
BIT
START
NEXT
BIT
Freescale Semiconductor
Figure
13-3.
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