S908AC4MDRE FREESCALE [Freescale Semiconductor, Inc], S908AC4MDRE Datasheet - Page 165
![no-image](/images/no-image-200.jpg)
S908AC4MDRE
Manufacturer Part Number
S908AC4MDRE
Description
M68HC08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.S908AC4MDRE.pdf
(274 pages)
- Current page: 165 of 274
- Download datasheet (4Mb)
Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode
sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD,
in the configuration register is 0, then the computer operating properly module (COP) is enabled and
remains active in wait mode.
Figure 14-15
14.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU
and peripherals. If OSCENINSTOP is set, BUSCLKX4 will remain running in STOP and can be used to
run the PWU. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles
down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do
not require long start-up times from stop mode.
Freescale Semiconductor
and
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt
ADDRESS BUS
ADDRESS BUS
1. RST is only available if the RSTEN bit in the CONFIG2 register is set.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
BUSCLKX4
DATA BUS
DATA BUS
Figure 14-16
MC68HC908QC16 • MC68HC908QC8 • MC68HC908QC4 Data Sheet, Rev. 5
RST
(1)
Figure 14-16. Wait Recovery from Internal Reset
$A6
$A6
Figure 14-15. Wait Recovery from Interrupt
show the timing for wait recovery.
$6E0B
$A6
$6E0B
$A6
$A6
$A6
CYCLES
$6E0C
32
NOTE
$01
$00FF
CYCLES
$0B
32
$00FE
$6E
RST VCT H
$00FD
RST VCT L
$00FC
Low-Power Modes
165
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