S29GL128S SPANSION [SPANSION], S29GL128S Datasheet - Page 81

• Manufacturer Part Number: S29GL128S
• Manufacturer: SPANSION [SPANSION]

March 16, 2012 S29GL_128S_01GS_00_06
Note:
1. Not 100% tested.
Note:
Back to Back operations, in which CE# remains Low between accesses, requires an address change to initiate the second access.
JEDEC
t
t
t
t
t
t
AVQV
ELQV
GLQV
AXQX
EHQZ
AVAV
Parameter
t
t
t
t
PACC
ASSB
Std
DQ15-DQ0
DQ15-DQ0
t
t
t
OEH
ACC
t
t
OH
RC
CE
OE
DF
Amax-A0
Amax-A0
OE#
OE#
CE#
CE#
Read Cycle Time
Address to Output Delay
Chip Enable to Output
Delay
Page Access Time
Output Enable to Output Delay
Output Hold time from addresses, CE# or
OE#, Whichever Occurs First
Chip Enable or Output Enable to Output
High-Z
Output Enable Hold Time
(Note 1)
Automatic Sleep to Standby time
Table 10.5 Read Operation V
Figure 10.5 Back to Back Read (t
Figure 10.6 Back to Back Read Operation (t
(Note 1)
D a t a
Description
(Note 1)
GL-S MirrorBit
S h e e t
tACC
tCE
tACC
tCE
CE# = V
OE# = V
OE# = V
Read
Toggle and
Data# Polling
(Note 1)
tOE
IL
IL
IL
®
IO
Family
tOE
= V
128 Mb, 256 Mb
512 Mb, 1 Gb
128 Mb, 256 Mb
512 Mb, 1 Gb
128 Mb, 256 Mb
512 Mb, 1 Gb
128 Mb, 256 Mb
512 Mb, 1 Gb
CE# = V
stable
CC
tOH
tOH
tOH
ACC
= 2.7V to 3.6V (-40°C to +105°C)
tOH
tOH
IL
) Operation Timing Diagram
Test Setup
, Address
RC
tRC
)Timing Diagram
Max
Max
Max
Max
Max
Max
Min
Min
Min
Min
Typ
100
100
100
100
15
Speed Option
110
110
110
110
110
110
110
20
15
25
15
10
0
0
5
8
tDF
tDF
tDF
120
120
120
120
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
81