S29GL128S SPANSION [SPANSION], S29GL128S Datasheet - Page 68

• Manufacturer Part Number: S29GL128S
• Manufacturer: SPANSION [SPANSION]

8.3
8.4
68
8.3.1
8.3.2
8.4.1
Power Conservation Modes
Read
Interface Standby
Automatic Sleep
Read With Output Disable
Standby is the default, low power, state for the interface while the device is not selected by the host for data
transfer (CE# = High). All inputs are ignored in this state and all outputs except RY/BY# are high impedance.
RY/BY# is a direct output of the EAC, not controlled by the Host Interface.
The automatic sleep mode reduces device interface energy consumption to the sleep level (I
the completion of a random read access time. The device automatically enables this mode when addresses
remain stable for t
system. Output of the data depends on the level of the OE# signal but, the automatic sleep mode current is
independent of the OE# signal level. Standard address access timings (t
addresses are changed. I
specification.
Automatic sleep helps reduce current consumption especially when the host system clock is slowed for power
reduction. During slow system clock periods, read and write cycles may extend many times their length
versus when the system is operating at high speed. Even though CE# may be Low throughout these
extended data transfer cycles, the memory device host interface will go to the Automatic Sleep current at t
+ 30 ns. The device will remain at the Automatic Sleep current for t
standby current level. This keeps the memory at the Automatic Sleep or standby power level for most of the
long duration data transfer cycles, rather than consuming full read power all the time that the memory device
is selected by the host system.
However, the EAC operates independent of the automatic sleep mode of the host interface and will continue
to draw current during an active Embedded Algorithm. Only when both the host interface and EAC are in their
standby states is the standby level current achieved.
When the CE# signal is asserted Low, the host system memory controller begins a read or write data transfer.
Often there is a period at the beginning of a data transfer when CE# is Low, Address is valid, OE# is High,
and WE# is High. During this state a read access is assumed and the Random Read process is started while
the data outputs remain at high impedance. If the OE# signal goes Low, the interface transitions to the
Random Read state, with data outputs actively driven. If the WE# signal is asserted Low, the interface
transitions to the Write state. Note, OE# and WE# should never be Low at the same time to ensure no data
bus contention between the host system and memory.
ACC
+ 30 ns. While in sleep mode, output data is latched and always available to the
CC6
in
DC Characteristics on page 74
GL-S MirrorBit
D a t a
®
Family
S h e e t
represents the automatic sleep mode current
ASSB
S29GL_128S_01GS_00_06 March 16, 2012
. Then the device will transition to the
ACC
or t
PACC
) provide new data when
CC6
) following
ACC