LTC693 LINER [Linear Technology], LTC693 Datasheet - Page 11

• Manufacturer Part Number: LTC693
• Description: Microprocessor Supervisory Circuits
• Manufacturer: LINER [Linear Technology]

A
5V
V
V
5V
IN
IN
+
PPLICATI
0.1 F
0.1 F
Figure 6. A Typical Nonvolatile CMOS RAM Application
6.5V
7.5V
R1
51k
R2
10k
10 F
3V
10 F
3V
Figure 8. Monitoring Unregulated DC Supply with the
LTC692/LTC693 Power Fail Comparator
Figure 9. Monitoring Regulated DC Supply
with the LTC692/LTC693 Power Fail Comparator
Figure 7. Write Protect for RAM with the LTC692
+
V
LT1086-5
IN
ADJ
V
V
V
BATT
CC
GND
V
V
OUT
V
LT1086-5
IN
BATT
CC
LTC693
O
LTC692
ADJ
GND
CE OUT
RESET
V
RESET
U
CE IN
OUT
V
RESET
OUT
+
V
S
OUT
10 F
I FOR ATIO
+
U
100 F
300k
R1
27k
R2
8.2k
R5
3.3k
20ns PROPAGATION DELAY
TO P
FROM DECODER
R3
+
2.7M
+
R3
5V
10k
10 F
R4
10 F
R4
10k
0.1 F
W
5V
0.1 F
0.1 F
0.1 F
TO P
CS
TO P
PFI
PFO
PFO
PFI
V
V
CC
CC
U
CS
V
LTC692
LTC693
LTC692
LTC693
CC
CS1
GND
CS2
GND
V
62512
LTC692/3 • F06
GND
RAM
LTC692/3 • F09
CC
LTC692/3 • F07
GND
LTC692/3 • F08
62128
RAM
Power Fail Warning
The LTC692/LTC693 generate a Power Failure Output
(PFO) for early warning of failure in the microprocessor's
power supply. This is accomplished by comparing the
Power Failure Input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The voltage
divider ratio can be chosen such that the voltage at the PFI
pin falls below 1.3V, several milliseconds before the 5V
supply falls below the maximum reset voltage threshold of
4.50V. PFO is normally used to interrupt the microproces-
sor to execute shutdown procedure between PFO and
RESET or RESET.
The power fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resis-
tor between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the
summing junction at the PFI pin.
When PFO output is high, the series combination of R3 and
R4 source current into the PFI summing junction.
Example 1: The circuit in Figure 8 demonstrates the use of
the power fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input V
a shutdown procedure is 8ms. Also, the noise of V
200mV. With these assumptions in mind, we can reason-
ably set V
maximum reset voltage threshold and the dropout voltage
of LT1086-5 (4.5V + 1.5V) and V
V
V = 1.3V 1+
Assuming R4
H
L
1.3V 1
L
= 7.25V which is 1.25V greater than the sum of
IN
is 100mV/ms and the total time to execute
R2
R1
R2
R1
–
R3,V
R3
1.3V(R3 R4)
R1
(5V – 1.3V)R1
HYSTERESIS
LTC692/LTC693
HYSTERESIS
5V
= 850mV.
R3
R1
11
IN
is