LTC693 LINER [Linear Technology], LTC693 Datasheet - Page 10

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LTC693

Manufacturer Part Number
LTC693
Description
Microprocessor Supervisory Circuits
Manufacturer
LINER [Linear Technology]
Datasheet

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If battery connections are made through long wires, a 10
to 100 series resistor and a 0.1 F capacitor are recom-
mended to prevent any overshoot beyond V
lead inductance (Figure 4).
LTC692/LTC693
A
Table 1 shows the state of each pin during battery backup.
When the battery switchover section is not used, connect
V
Memory Protection
The LTC693 includes memory protection circuitry which
ensures the integrity of the data in memory by preventing
write operations when V
additional pins, CE IN and CE OUT, control the Chip Enable
or Write inputs of CMOS RAM. When V
follows CE IN with a typical propagation delay of 20ns.
When V
CE OUT is forced high, independent of CE IN. CE OUT is an
10
BATT
PPLICATI
Figure 4. 10 /0.1 F combination eliminates inductive
overshoot and prevents spurious resets during battery
replacement.
to GND and V
CC
falls below the reset voltage threshold or V
CE OUT
CE IN
V
10
O
CC
V
OUT
U
OUT
S
= V
3.9M
to V
BATT
I FOR ATIO
CC
U
CC
is at an invalid level. Two
.
0.1µF
W
Figure 5. Timing Diagram for CE IN and CE OUT
V
BATT
CC
LTC692
LTC693
GND
is 5V, CE OUT
CC
LTC692/3 • F04
due to the
U
V1
BATT
,
V2
alternative signal to drive the CE, CS, or Write input of
battery backed up CMOS RAM. CE OUT can also be used
to drive the Store or Write input of an EEPROM, EAROM or
NOVRAM to achieve similar protection. Figure 5 shows the
timing diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor's address
decoder output. Figure 6 shows a typical nonvolatile
CMOS RAM application.
Memory protection can also be achieved with the LTC692
by using RESET as shown in Figure 7.
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL
V
V
V
BATT ON
PFI
PFO
RESET
RESET
LOW LINE Logic low
WDI
WDO
CE IN
CE OUT
OSC IN
OSC SEL
CC
OUT
BATT
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
STATUS
Logic low
Logic high. The open-circuit output voltage is equal to V
Logic high. The open-circuit output voltage is equal to V
C2 monitors V
V
The supply current is 1 A maximum.
Logic high. The open-circuit output voltage is equal to V
Power Failure Input is ignored.
Logic low
Watchdog Input is ignored.
Logic high. The open-circuit output voltage is equal to V
Chip Enable Input is ignored.
OSC IN is ignored.
OSC SEL is ignored.
OUT
is connected to V
CC
for active switchover.
BATT
V
OUT
through an internal PMOS switch.
LTC692/3 • F05
= V
BATT
OUT
OUT
OUT
OUT
.
.
.
.

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