XC3030L Xilinx, XC3030L Datasheet - Page 7

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. The
XC3020 has 64 such blocks arranged in 8 rows and 8
columns. The XACT development system is used to com-
pile the configuration data which is to be loaded into the
internal configuration memory to define the operation and
interconnection of each block. User definition of CLBs and
their interconnecting networks may be done by automatic
translation from a schematic-capture logic diagram or
optionally by installing library or user macros.
Figure 4. Configurable Logic Block. Each CLB includes a combinatorial logic section, two flip-flops and a program
memory controlled multiplexer selection of function. It has. five logic variable inputs A, B, C, D, and E
ENABLE CLOCK
VARIABLES
DATA IN
DIRECT
CLOCK
RESET
LOGIC
DI
A
B
C
D
E
EC
K
RD
QX
QY
COMBINATORIAL
(GLOBAL RESET)
FUNCTION
1 (ENABLE)
0 (INHIBIT)
G
F
a direct data in DI
an enable clock EC
a clock (invertible) K
an asynchronous direct RESET RD
two outputs X and Y
2-109
F
DIN
G
F
DIN
G
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 4. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function F or G outputs of the combinatorial logic, or the
block input, DI. Both flip-flops in each CLB share the
MUX
MUX
0
1
0
1
D
D
RD
RD
Q
Q
QX
F
G
QY
CLB OUTPUTS
X
Y
X3032