XC3030L Xilinx, XC3030L Datasheet - Page 13

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

nect should be used to maximize the speed of high-
performance portions of logic. Where logic blocks are
adjacent to IOBs, direct connect is provided alternately to
the IOB inputs (I) and outputs (O) on all four edges of the
die. The right edge provides additional direct connects
from CLB outputs to adjacent IOBs. Direct interconnec-
tions of IOBs with CLBs are shown in Figure 12.
Longlines
The Longlines bypass the switch matrices and are in-
tended primarily for signals that must travel a long dis-
tance, or must have minimum skew among multiple des-
tinations. Longlines, shown in Figure 13, run vertically and
horizontally the height or width of the interconnect area.
Each interconnection column has three vertical Longlines,
and each interconnection row has two horizontal Lon-
glines. Two additional Longlines are located adjacent to
the outer sets of switching matrices. In devices larger than
the XC3020, two vertical Longlines in each column are
connectable half-length lines. On the XC3020, only the
outer Longlines are connectable half-length lines.
Longlines can be driven by a logic block or IOB output on
a column-by-column basis. This capability provides a
common low skew control or clock line within each column
of logic blocks. Interconnections of these Longlines are
shown in Figure 14. Isolation buffers are provided at each
input to a Longline and are enabled automatically by the
development system when a connection is made.
Figure 13. Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in each row and
column. The global buffer in the upper left die corner drives a common line throughout the LCA device.
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A buffer in the upper left corner of the LCA chip drives a
global net which is available to all K inputs of logic blocks.
Using the global buffer for a clock signal provides a skew-
free, high fan-out, synchronized clock for use at any or all
of the IOBs and CLBs. Configuration bits for the K input to
each logic block can select this global line or another
routing resource as the clock source for its flip-flops. This
net may also be programmed to drive the die edge clock
lines for IOB use. An enhanced speed, CMOS threshold,
direct access to this buffer is available at the second pad
from the top of the left die edge.
A buffer in the lower right corner of the array drives a
horizontal Longline that can drive programmed connec-
tions to a vertical Longline in each interconnection column.
This alternate buffer also has low skew and high fan-out.
The network formed by this alternate buffer’s Longlines
can be selected to drive the K inputs of the CLBs. CMOS
threshold, high speed access to this buffer is available from
the third pad from the bottom of the right die edge.
Internal Busses
A pair of 3-state buffers, located adjacent to each CLB,
permits logic to drive the horizontal Longlines. Logic op-
eration of the 3-state buffer controls allows them to imple-
ment wide multiplexing functions. Any 3-state buffer input
can be selected as drive for the horizontal long-line bus by
applying a Low logic level on its 3-state control line. See
Figure 15a. The user is required to avoid contention which
can result from multiple drivers with opposing logic levels.
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