XC3030L Xilinx, XC3030L Datasheet - Page 25

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

Master Parallel Mode Programming Switching Characteristics
Notes: 1. At power-up, V
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
RCLK
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode
(output)
(output)
(output)
(output)
A0-A15
D0-D7
DOUT
RCLK
CCLK
delayed by holding RESET Low until V
>100 ms, or a non-monotonically rising V
level on RESET and D/P after V
devices is High.
To address valid
To data setup
To data hold
RCLK High
RCLK Low
Description
CC
must rise from 2.0 V to V
CC
has reached 4.0 V (2.5 V for the XC3000L).
CC
1
2
3
CC
Symbol
has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
may require a >6- s High level on RESET, followed by a >6- s Low
Address for Byte n
min in less than 25 ms. If this is not possible, configuration can be
T
T
T
T
T
RAC
DRC
RCD
RCH
RCL
2-127
7 CCLKs
2 T
Byte
DRC
600
Min
60
0
0
4.0
Byte n - 1
D6
Address for Byte n + 1
1 T
3 T
CCLK
RAC
RCD
200
Max
CC
D7
rise time of
Units
X5380
ns
ns
ns
ns
s