EPM570 Altera, EPM570 Datasheet - Page 71

• Manufacturer Part Number: EPM570
• Description: MAX II Device Family
• Manufacturer: Altera

Figure 5–1. MAX II Device Timing Model
Altera Corporation
December 2004
I/O Pin
INPUT
I/O Input Delay
t
IN
Input Routing
Global Input Delay
Memory
Delay
Flash
User
t
DL
t
GLOB
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Refer to the chapter on Understanding
Timing in MAX II Devices for more information.
This section describes and specifies the performance, internal, external,
and UFM timing specifications. All specifications are representative of
worst-case supply voltage and junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The
Quartus
compilation if the timing models are preliminary.
status of the MAX II device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Data-In/LUT Chain
®
To Adjacent LE
II software issues an informational message during the design
Core Version a.b.c variable
Register Control
LUT Delay
Logic Element
Delay
t
LUT
t
C
t
R4
t
t
t
t
PRE
CLR
CO
t
SU
H
Register Delays
t
C4
Data-Out
From Adjacent LE
MAX II Device Handbook, Volume 1
Output Routing
DC & Switching Characteristics
t
Delay
FASTIO
t
IODR
t
IOE
Table 5–13
Output & Output Enable
Data Delay
Output
Delay
t
t
t
OD
XZ
ZX
shows the
I/O Pin
5–9