EPM570 Altera, EPM570 Datasheet - Page 51

• Manufacturer Part Number: EPM570
• Description: MAX II Device Family
• Manufacturer: Altera

Altera Corporation
December 2004
f
debugging cycles. The logic, circuitry, and interconnects in the MAX II
architecture are configured with flash-based SRAM configuration
elements. These SRAM elements require configuration data to be loaded
each time the device is powered. The process of loading the SRAM data
is called configuration. The on-chip configuration flash memory (CFM)
block stores the SRAM element’s configuration data. The CFM block
stores the design’s configuration pattern in a reprogrammable flash array.
During ISP, the MAX II JTAG and ISP circuitry programs the design
pattern into the CFM block’s non-volatile flash array.
The MAX II JTAG and ISP controller internally generate the high
programming voltages required to program the CFM cells, allowing in-
system programming with any of the recommended operating external
voltage supplies (i.e., 3.3 V/2.5 V or 1.8 V for the MAX IIG devices). ISP
can be performed anytime after V
fully powered and the device has completed the configuration power-up
time. By default, during in-system programming, the I/O pins are tri-
stated and weakly pulled-up to V
system programming clamp and real-time ISP feature allows user control
of I/O state or behavior during ISP.
For more information, refer to
page 3–7
These devices also offer an ISP_DONE bit that provides safe operation
when in-system programming is interrupted. This ISP_DONE bit, which
is the last bit programmed, prevents all I/O pins from driving until the
bit is programmed.
IEEE 1532 Support
The JTAG circuitry and ISP instruction set in MAX II devices is compliant
to the IEEE 1532-2002 programming specification. This provides
industry-standard hardware and software for in-system programming
among multiple vendor programmable logic devices (PLDs) in a JTAG
chain.
The MAX II 1532 BSDL files will be released on the Altera web site when
available.
Jam Standard Test & Programming Language (STAPL)
The Jam STAPL JEDEC standard, JESD71, can be used to program MAX II
devices with in-circuit testers, PCs, or embedded processors. The Jam
byte code is also supported for MAX II devices. These software
programming protocols provide a compact embedded solution for
programming MAX II devices.
and
Core Version a.b.c variable
“Real-Time ISP” on page
“In-System Programming Clamp” on
CCIO
CCINT
to eliminate board conflicts. The in-
JTAG & In-System Programmability
MAX II Device Handbook, Volume 1
3–7.
and all V
CCIO
banks have been
3–5