EPM2210 Altera Corporation, EPM2210 Datasheet - Page 7

• Manufacturer Part Number: EPM2210
• Description: (EPMxxxx) JTAG & In-System Programmability
• Manufacturer: Altera Corporation

Functional
Description
Altera Corporation
December 2004
MII51002-1.2
MAX
architecture to implement custom logic. Column and row interconnect
provide signal interconnects between the logic array blocks (LABs).
The logic array consists of LABs, with 10 logic elements (LEs) in each
LAB. An LE is a small unit of logic providing efficient implementation of
user logic functions. LABs are grouped into rows and columns across the
device. The MultiTrack™ interconnect provides fast granular timing
delays between LABs. The fast routing between LEs provides minimum
timing delay for added levels of logic versus globally routed interconnect
structures.
The MAX II device I/O pins are fed by an I/O element (IOE) located at
the ends of LAB rows and columns around the periphery of the device.
Each IOE contains a bidirectional I/O buffer with several advanced
features. I/O pins support Schmitt trigger inputs and various single-
ended standards, such as 33-MHz, 32-bit PCI and LVTTL.
MAX II devices provide a global clock network. The global clock network
consists of four global clock lines that drive throughout the entire device,
providing clocks for all resources within the device. The global clock lines
can also be used for control signals such as clear, preset, or output enable.
Figure 2–1
®
II devices contain a two-dimensional row- and column-based
Core Version a.b.c variable
shows a functional block diagram of the MAX II device.
Chapter 2. MAX II
Architecture
Preliminary
2–1