EPM2210 Altera Corporation, EPM2210 Datasheet - Page 40

• Manufacturer Part Number: EPM2210
• Description: (EPMxxxx) JTAG & In-System Programmability
• Manufacturer: Altera Corporation

I/O Structure
Figure 2–23. MAX II I/O Banks for EPM1270 & EPM2210
Notes to
(1)
(2)
2–34
MAX II Device Handbook, Volume 1
Figure 2–23
Figure 2–23
I/O Bank 1
Figure
2–23:
is a top view of the silicon die.
is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
Each I/O bank has dedicated VCCIO pins which determine the voltage
standard support in that bank. A single device can support 1.5-V, 1.8-V,
2.5-V, and 3.3-V interfaces; each individual bank can support a different
standard. Each I/O bank can support multiple standards with the same
V
can support LVTTL, LVCMOS, and 3.3-V PCI. V
input and output buffers in MAX II devices.
The JTAG pins for MAX II devices are dedicated pins that cannot be used
as regular I/O pins. The pins TMS, TDI, TDO, and TCK support all the I/O
standards shown in
reside in Bank 1 for all MAX II devices and their I/O standard support is
controlled by the V
CCIO
for input and output pins. For example, when V
Core Version a.b.c variable
All I/O Banks Support
■
■
■
■
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
I/O Bank 2
I/O Bank 4
CCIO
Table 2–4 on page 2–32
setting for Bank 1.
Notes
(1),
(2)
except for PCI. These pins
CCIO
I/O Bank 3
powers both the
CCIO
Altera Corporation
Also Supports
the 3.3-V PCI
I/O Standard
is 3.3 V, Bank 3
December 2004