EPM2210 Altera Corporation, EPM2210 Datasheet - Page 57

• Manufacturer Part Number: EPM2210
• Description: (EPMxxxx) JTAG & In-System Programmability
• Manufacturer: Altera Corporation

Figure 4–1. Hot Socketing Circuit Block Diagram for MAX II Devices
Altera Corporation
December 2004
Resistor
Pull-Up
Weak
PAD
Hot Socketing Feature Implementation in MAX II Devices
The hot socketing feature turns off (tri-states) the output buffer during the
power-up event (either V
hot-socket circuit generates an internal HOTSCKT signal when either
V
off the output buffer to make sure that no DC current (except for weak
pull-up leaking) leaks through the pin. When V
V
is released and device configuration is complete.
Each I/O and clock pin has the following circuitry, as shown in
Figure
The POR circuit monitors V
pins tri-stated until the device has completed its flash memory
configuration of the SRAM logic. The weak pull-up resistor (R) from the
I/O pin to V
floating. The 3.3-V tolerance control circuit permits the I/O pins to be
driven by 3.3 V before V
the I/O pins from driving out when the device is not fully powered or
CCINT
CC
may still be relatively low even after the power-on reset (POR) signal
4–1.
or V
V
CCIO
Core Version a.b.c variable
CCIO
CCIO
is below the threshold voltage. The HOTSCKT signal cuts
is enabled during download to keep the I/O pins from
Hot Socketing & Power-On Reset in MAX II Devices
CCIO
Input Buffer
to Logic Array
CCINT
Tolerance
Voltage
Control
CCINT
and/or V
or V
and V
Output Enable
CCIO
CCINT
CCIO
MAX II Device Handbook, Volume 1
supplies) or power down. The
voltage levels and keeps I/O
are powered, and it prevents
Hot Socket
CC
Power On
Monitor
Reset
ramps up very slowly,
4–3