CY7C1329-75AC Cypress Semiconductor, CY7C1329-75AC Datasheet - Page 6

• Manufacturer Part Number: CY7C1329-75AC
• Description: 64K x 32 Synchronous-Pipelined Cache RAM
• Manufacturer: Cypress Semiconductor

Write Cycle Descriptions
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
Ambient Temperature with
Power Applied
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
Notes:
4.
5.
6.
7.
8.
Read
Read
Write Byte 0 - DQ
Write Byte 1 - DQ
Write Bytes 1, 0
Write Byte 2 - DQ
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 - DQ
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
Write All Bytes
X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW.
The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a “don't care” for the remainder of the write cycle.
OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ=High-Z when OE is inactive or
when the device is deselected, and DQ=data when OE is active.
Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
T
A
is the case temperature.
[7]
[7]
Function
[7:0]
[15:8]
[23:16]
[31:24]
DD
Relative to GND
[4,5,6]
0.5V to V
0.5V to V
65°C to +150°C
55°C to +125°C
0.5V to +4.6V
DDQ
DDQ
GW
+ 0.5V
+ 0.5V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
6
BWE
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Com’l
Range
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
Temperature
0°C to +70°C
BW
Ambient
X
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
3
[3:0]
[8]
. Writes may occur only on subsequent clocks
BW
X
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
2
5%/+10%
3.3V
V
DD
BW
CY7C1329
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
1
5%/+10%
V
3.3V
DDQ
BW
X
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0