CY7C1329-75AC Cypress Semiconductor, CY7C1329-75AC Datasheet

CY7C1329-75AC

Manufacturer Part Number

CY7C1329-75AC

Description

64K x 32 Synchronous-Pipelined Cache RAM

Manufacturer

Cypress Semiconductor

Datasheet

1.CY7C1329-75AC.pdf (14 pages)

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Features

Functional Description

The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined

cache SRAM designed to support zero wait state secondary

cache with minimal glue logic.

Intel and Pentium are registered trademarks of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Logic Block Diagram

Cypress Semiconductor Corporation

• Supports 133-MHz bus for Pentium® and PowerPC™

• Fully registered inputs and outputs for pipelined

• 64K x 32 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times

• User-selectable burst counter supporting Intel®

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100 TQFP pinout

• “ZZ” Sleep Mode option and Stop Clock option

operations with zero wait states

operation

Pentium interleaved or linear burst sequences

— 4.2 ns (for 133-MHz device)

— 5.5 ns (for 100-MHz device)

— 7.0 ns (for 75-MHz device

ADSP

ADSC

BWE

ADV

CLK

[15:0]

64K x 32 Synchronous-Pipelined Cache RAM

MODE

[1:0]

•

)

3901 North First Street

CLR

ENABLE DELAY

CLK

BYTEWRITE

REGISTERS

BYTEWRITE

REGISTERS

BYTEWRITE

REGISTERS

BYTEWRITE

DQ[23:16]

DQ[31:24]

COUNTER

DQ[15:8]

CONTROL

ADDRESS

DQ[7:0]

ENABLE

SLEEP

BURST

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise is 4.2 ns (133-MHz

device).

The CY7C1329 supports either the interleaved burst se-

quence used by the Intel Pentium processor or a linear burst

sequence used by processors such as the PowerPC. The burst

sequence is selected through the MODE pin. Accesses can

be initiated by asserting either the Processor Address Strobe

(ADSP) or the Controller Address Strobe (ADSC) at clock rise.

Address advancement through the burst sequence is con-

trolled by the ADV input. A 2-bit on-chip wraparound burst

counter captures the first address in a burst sequence and

automatically increments the address for the rest of the burst

access.

Byte write operations are qualified with the four Byte Write

Select (BW

all byte write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed write cir-

cuitry.

Three synchronous Chip Selects (CE

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to provide prop-

er data during depth expansion, OE is masked during the first

clock of a read cycle when emerging from a deselected state.

•

[3:0]

San Jose

) inputs. A Global Write Enable (GW) overrides

•

CLK

REGISTERS

OUTPUT

CA 95134

MEMORY

64KX32

ARRAY

, CE

CY7C1329

•

CLK

REGISTERS

, CE

August 6, 1999

INPUT

408-943-2600

) and an

[31:0]

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