CY7C1329-75AC Cypress Semiconductor, CY7C1329-75AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1329-75AC
• Description: 64K x 32 Synchronous-Pipelined Cache RAM
• Manufacturer: Cypress Semiconductor

Linear Burst Sequence
ZZ Mode Electrical Characteristics
Cycle Descriptions
A
00
01
10
11
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “sleep”
Notes:
1.
2.
3.
[1:0]
Address
Next Cycle
Parameter
First
X=”Don't Care”, 1=HIGH, 0=LOW.
Write is defined by BWE, BW
The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
t
I
ZZREC
DDZZ
t
ZZS
A
01
10
11
00
[1:0]
Address
Second
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
None
Add. Used
Device operation to
ZZ recovery time
standby current
Snooze mode
[1,2,3]
Description
[3:0]
ZZ
, and GW. See Write Cycle Descriptions table.
A
10
11
00
01
[1:0]
Address
Third
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Test Conditions
ZZ > V
ZZ > V
CE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
A
11
00
01
10
ZZ < 0.2V
3
[1:0]
Address
Fourth
DD
DD
CE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
0.2V
0.2V
2
CE
5
1
0
0
0
0
0
0
X
X
1
1
X
X
1
1
X
1
0
X
1
X
1
X
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE
duration of t
1
1
, CE
2t
ADSP
Min
CYC
X
0
0
1
1
0
1
X
X
1
1
X
X
1
X
1
1
X
1
X
X
1
1
2
, CE
ZZREC
3,
ADSP, and ADSC must remain inactive for the
ADSC
X
X
X
X
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
after the ZZ input returns LOW.
ADV
2t
Max
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
1
0
0
1
1
CYC
3
OE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
CY7C1329
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Unit
mA
ns
ns
X
X
X
X
X
X
read
read
read
read
read
read
read
read
read
write
write
write
write
write
write
write
X
Write