CY7C1329-75AC Cypress Semiconductor, CY7C1329-75AC Datasheet - Page 11

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CY7C1329-75AC

Manufacturer Part Number
CY7C1329-75AC
Description
64K x 32 Synchronous-Pipelined Cache RAM
Manufacturer
Cypress Semiconductor
Datasheet
Switching Waveforms
Read/Write Cycle Timing
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
CE
Data-
In/Out
CLK
ADSP
ADV
GW
WE
CE
CE
ADSC
ADD
OE
3
1
2
t
t
t
CES
ADS
CES
t
AS
t
CES
RD1
t
ADVS
Single Read
t
CEH
t
t
CYC
t
t
t
t
CEH
CEH
ADH
AH
WS
t
t
[14,15,16, 17]
OELZ
t
WH
t
CO
t
ADVH
(continued)
ADS
t
DOE
WD2
1a
Out
1a
t
Single Write
CH
t
t
OEHZ
ADH
t
CL
= DON’T CARE
2a
In
t
RD3
WS
t
WH
See Note 17
11
ADSP ignored with CE
2a
Out
= UNDEFINED
CE
Burst Read
1
t
masks ADSP
DS
3a
Out
t
DH
Out
3b
1
inactive
Pipelined Read
Out
3c
t
DOH
Out
3d
CY7C1329
Unselected
T
CHZ

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