CY7C09279 Cypress Semiconductor, CY7C09279 Datasheet - Page 8

• Manufacturer Part Number: CY7C09279
• Description: (CY7C09279 - CY7C09289) 32K/64K X 16/18 Synchronous Dual Port Static RAM
• Manufacturer: Cypress Semiconductor

Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V
Read Cycle for Pipelined Operation (FT/PIPE = V
Notes:
Document #: 38-06040 Rev. **
14. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
15. ADS = V
16. The output is disabled (high-impedance state) by CE
17. Addresses do not have to be accessed sequentially since ADS = V
ADDRESS
ADDRESS
DATA
DATA
IL
CLK
R/W
CE
CE
OUT
CLK
R/W
CE
CE
OE
, CNTEN and CNTRST = V
OUT
OE
0
1
0
1
t
t
t
t
t
t
SC
SW
SA
SC
SW
SA
A
A
n
n
t
t
t
t
t
t
t
HC
HW
HA
t
CH2
HC
HW
HA
CH1
IH
t
1 Latency
CKLZ
.
t
CD1
t
CYC2
t
CYC1
t
CKLZ
t
CL2
t
0
CL1
=V
IH
A
A
or CE
n+1
n+1
IH
IL
)
[14, 15, 16, 17]
1
)
t
Q
IL
DC
[14, 15, 16, 17]
= V
t
n
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
CD2
IL
following the next rising edge of the clock.
Q
A
n
A
n+2
n+2
Q
t
OHZ
n+1
t
DC
Q
t
t
t
SC
SC
t
OE
n+1
t
OLZ
OHZ
A
A
n+3
CY7C09279/89
CY7C09379/89
n+3
t
OLZ
Q
t
DC
t
n+2
t
HC
HC
t
OE
t
CKHZ
Page 8 of 18
Q
n+2