CYWUSB6932-48LFXC Cypress Semiconductor, CYWUSB6932-48LFXC Datasheet - Page 20

• Manufacturer Part Number: CYWUSB6932-48LFXC
• Description: WirelessUSB LS 2.4-GHz DSSS Radio SoC
• Manufacturer: Cypress Semiconductor

Document 38-16007 Rev. *G
Bit
7
6
5:0
Bit
7:6
5:0
Bit
7
6:0
Reg Power
Reserved
Control
Name
Reserved
Clock Output
Disable
Crystal Adjust
Name
VCO Slope Enable
(Write-Only)
Reserved
Name
Reg Power
Control
Reserved
7
7
7
VCO Slope Enable
Addr: 0x2E
Addr: 0x24
Addr: 0x26
Clock Output
Description
When set, this bit disables unused circuitry and saves radio power. The user must set Reg 0x20, bit 6=1 to enable writes
to Reg 0x2E. The application MCU must set this bit during initialization.
These bits are reserved and should be written with zeroes.
Disable
6
6
6
Description
The Voltage Controlled Oscillator (VCO) Slope Enable bits are used to specify the amount of variance automatically
added to the VCO.
These bits are undefined for read operations.
These bits are reserved and should be written with zeroes.
Description
This bit is reserved and should be written with zero.
The Clock Output Disable bit disables the 13 MHz clock driven on the X13OUT pin.
If the 13 MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by -4 dBm on channels
5+13 n . By default the 13 MHz clock output pin is enabled. This pin is useful for adjusting the 13 MHz clock, but it
interfere with every 13th channel beginning with 2.405GHz channel. Therefore, it is recommended that the 13 MHz
clock output pin be disabled when not in use.
The Crystal Adjust value is used to calibrate the on-chip parallel load capacitance supplied to the crystal. Each
increment of the Crystal Adjust value typically adds 0.135 pF of parallel load capacitance. The total range is 8.5
pF, starting at 8.65 pF. These numbers do not include PCB parasitics, which can add an additional 1-2 pF.
11 = -5/+5 VCO adjust. The application MCU must configure this option during initialization.
10 = -2/+3 VCO adjust.
01 = Reserved.
00 = No VCO adjust.
1 = No 13 MHz clock driven externa
0 = 13 MHz clock driven externally
5
5
5
Figure 7-27. Reg Power Control
Figure 7-26. VCO Calibration
Figure 7-25. Crystal Adjust
REG_CRYSTAL_ADJ
4
REG_VCO_CAL
4
4
REG_PWR_CTL
.
ll
y
.
Reserved
3
3
3
Crystal Adjust
Reserved
2
2
2
1
1
1
CYWUSB6932
CYWUSB6934
Default: 0x00
Default: 0x00
Default: 0x00
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