CYWUSB6932-48LFXC Cypress Semiconductor, CYWUSB6932-48LFXC Datasheet - Page 14

• Manufacturer Part Number: CYWUSB6932-48LFXC
• Description: WirelessUSB LS 2.4-GHz DSSS Radio SoC
• Manufacturer: Cypress Semiconductor

Document 38-16007 Rev. *G
Bit
7:4
3
2
1
0
Addr: 0x0D
Name
Reserved
Underflow
Overflow
Done
Empty
7
Description
These bits are reserved and should be written with zeroes.
The Underflow bit is used to enable the interrupt associated with an underflow condition associated with the Transmit
SERDES Data register (Reg 0x0F)
An underflow condition occurs when attempting to transmit while the Transmit SERDES Data register (Reg 0x0F) does not
have any data.
The Overflow bit is used to enabled the interrupt associated with an overflow condition with the Transmit SERDES Data
register (0x0F).
An overflow condition occurs when attempting to write new data to the Transmit SERDES Data register (Reg 0x0F) before
the preceding data has been transferred to the transmit shift register.
The Done bit is used to enable the interrupt that signals the end of the transmission of data.
The Done condition occurs when the Transmit SERDES Data register (Reg 0x0F) has transmitted all of its data and there
is no more data for it to transmit.
The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is empty.
The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit buffer and
it's safe to load the next byte
1 = Underflow interrupt enabled.
0 = Underflow interrupt disabled.
1 = Overflow interrupt enabled.
0 = Overflow interrupt disabled.
1 = Done interrupt enabled.
0 = Done interrupt disabled.
1 = Empty interrupt enabled.
0 = Empty interrupt disabled.
6
Reserved
Figure 7-12. Transmit SERDES Interrupt Enable
5
REG_TX_INT_EN
4
Underflow
3
Overflow
2
Done
1
CYWUSB6932
CYWUSB6934
Default: 0x00
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Empty
0