LTC3856 LINER [Linear Technology], LTC3856 Datasheet - Page 35

• Manufacturer Part Number: LTC3856
• Description: 2-Phase Synchronous Step-Down DC/DC Controller with Diffamp
• Manufacturer: LINER [Linear Technology]

applicaTions inForMaTion
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 17. Check the following in the
PC layout:
1. Are the signal and power ground paths Kelvin connected?
2. Does the IC DIFFP pin connect to the (+) plates of
3. Are the SENSE
Keep the SGND at one end of a printed circuit path thus
preventing MOSFET currents from traveling under the
IC. The INTV
immediately adjacent to the IC between the INTV
and PGND plane. A 1µF ceramic capacitor of the X7R or
X5R type is small enough to fit very close to the IC to
minimize the ill effects of the large current pulses drawn
to drive the bottom MOSFETs. An additional 5µF to 10µF
of ceramic, tantalum or other very low ESR capacitance
is recommended in order to keep the internal IC supply
quiet. The power ground returns to the sources of the
bottom N-channel MOSFETs, anodes of the Schottky
diodes and (–) plates of C
lead lengths as possible.
C
the DIFFP and V
possible to the IC.
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE
SENSE
to the pins of the IC. Connect the SENSE
pins to the pads of the sense resistor as illustrated in
Figure 1.
OUT
? A 30pF to 300pF feedforward capacitor between
–
for each channel should be as close as possible
CC
–
decoupling capacitor should be placed
FB
and SENSE
pins should be placed as close as
IN
, which should have as short
+
printed circuit traces for
–
and SENSE
CC
+
and
pin
+
4. Do the (+) plates of C
5. Keep the switching nodes, SWn, BOOSTn and TGn away
6. Use a low impedance source such as a logic gate to drive
7. The 47pF to 330pF ceramic capacitor between the I
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.
from sensitive small-signal nodes (SENSE
DIFFP , DIFFN, V
and TGn printed circuit traces should be routed away
and separated from the IC and especially the “quiet”
side of the IC. Separate the high dv/dt traces from sensi-
tive small-signal nodes with ground traces or ground
planes.
the PLLIN pin and keep the lead as short as possible.
pin and signal ground should be placed as close as pos-
sible to the IC. Figure 17 illustrates all branch currents
in a 2-phase switching regulator. It becomes very clear
after studying the current waveforms why it is critical to
keep the high switching current paths to a small physical
size. High electric and magnetic fields will radiate from
these loops just as radio stations transmit signals. The
output capacitor ground should return to the negative
terminal of the input capacitor and not share a common
ground path with any switched current paths. The left
half of the circuit gives rise to the noise generated by
a switching regulator. The ground terminations of the
synchronous MOSFETs and Schottky diodes should
return to the bottom plate(s) of the input capacitor(s)
with a short isolated PC trace since very high switched
currents are present. External OPTI-LOOP
tion allows overcompensation for PC layouts which are
not optimized, but this is not the recommended design
procedure.
FB
, ITEMP). Ideally the SWn, BOOSTn
PWR
connect to the drains of the
LTC3856
®
compensa-
+
, SENSE

3856f
TH
–
,