LTC3856 LINER [Linear Technology], LTC3856 Datasheet - Page 30

• Manufacturer Part Number: LTC3856
• Description: 2-Phase Synchronous Step-Down DC/DC Controller with Diffamp
• Manufacturer: LINER [Linear Technology]

LTC3856
applicaTions inForMaTion
Phase-Locked Loop and Frequency Synchronization
The LTC3856 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (V
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the PLLIN pin. The turn-on of the
second phase’s top MOSFETs is thus 180° out-of-phase
with the external clock, and so on. The phase detector is
an edge-sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit a false lock
to harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal filter
network. There is a precision 10µA of current flowing out
of FREQ pin. This allows the user to use a single resistor to
SGND to set the switching frequency when no external clock
0
Figure 15. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
900
800
700
600
500
400
300
200
100
0
0
FREQ/PLLFLTR PIN VOLTAGE (V)
0.5
1
1.5
2
CO
3856 F15
) and a phase
2.5
is applied to the PLLIN pin. The internal switch between
the FREQ pin and the integrated PLL filter network is on,
allowing the filter network to be pre-charged at the same
voltage as of the FREQ pin. The relationship between the
voltage on the FREQ pin and operating frequency is shown
in Figure 15 and specified in the Electrical Characteristics
table. If an external clock is detected on the PLLIN pin, the
internal switch mentioned above turns off and isolates the
influence of the FREQ pin. Note that the LTC3856 can only
be synchronized to an external clock whose frequency is
within range of the LTC3856’s internal V
anteed to be between 250kHz and 770kHz. A simplified
block diagram is shown in Figure 16.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
OSCILLATOR
EXTERNAL
Figure 16. Phase-Locked Loop Block Diagram
PLLIN
FREQUENCY
DETECTOR
DIGITAL
PHASE/
SYNC
OSC
2.4V
, then current is sourced
5V
CO
FREQ
. This is guar-
R
SET
V
CO
3856 F16
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