LTC2226 LINER [Linear Technology], LTC2226 Datasheet - Page 21

• Manufacturer Part Number: LTC2226
• Description: 12-Bit, 65/40/25Msps Low Power 3V ADCs
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2228/LTC2227/
LTC2226 is 65Msps (LTC2228), 40Msps (LTC2227), and
25Msps (LTC2226). For the ADC to operate properly, the
CLK signal should have a 50% (±5%) duty cycle. Each
half cycle must have at least 7.3ns (LTC2228), 11.8ns
(LTC2227), and 18.9ns (LTC2226) for the ADC internal cir-
cuitry to have enough settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3V
The lower limit of the LTC2228/LTC2227/LTC2226 sample
rate is determined by droop of the sample-and-hold circuits.
The pipelined architecture of this ADC relies on storing
analog signals on small-valued capacitors. Junction leak-
age will discharge the capacitors. The specifi ed minimum
operating frequency for the LTC2228/LTC2227/LTC2226
is 1Msps.
DD
or 2/3V
DD
LATCH
LTC2228/27/26
FROM
DATA
using external resistors.
OE
PREDRIVER
LOGIC
V
DD
Figure 14. Digital Output Buffer
V
DD
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overfl ow bit.
Table 1. Output Codes vs Input Voltage
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
LTC2228/LTC2227/LTC2226
>+1.000000V
<–1.000000V
(2V RANGE)
A
+0.999512V
+0.999024V
+0.000488V
–0.000488V
–0.000976V
–0.999512V
–1.000000V
0.000000V
IN
+
OV
– A
DD
IN
–
43Ω
222876 F14
OV
OGND
OF
1
0
0
0
0
0
0
0
0
1
DD
TYPICAL
DATA
OUTPUT
0.5V
TO 3.6V
0.1μF
(OFFSET BINARY)
1111 1111 1111
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
D11-D0
DD
and OGND, isolated
(2’s COMPLEMENT)
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
D11-D0
21
222876fb