LTC2226 LINER [Linear Technology], LTC2226 Datasheet - Page 20

• Manufacturer Part Number: LTC2226
• Description: 12-Bit, 65/40/25Msps Low Power 3V ADCs
• Manufacturer: LINER [Linear Technology]

LTC2228/LTC2227/LTC2226
APPLICATIONS INFORMATION
Input Range
The input range can be set based on the application.
The 2V input range will provide the best signal-to-noise
performance while maintaining excellent SFDR. The 1V
input range will have better SFDR performance, but the
SNR will degrade by 3.8dB. See the Typical Performance
Characteristics section.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or
TTL level signal. A sinusoidal clock can also be used
along with a low jitter squaring circuit before the CLK pin
(Figure 11).
The noise performance of the LTC2228/LTC2227/LTC2226
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digi-
tizing high input frequencies, use as large an amplitude
as possible. Also, if the ADC is clocked with a sinusoidal
signal, fi lter the CLK signal to reduce wideband noise and
distortion products generated by the source.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
20
CLOCK INPUT
SINUSOIDAL
Figure 11. Single-Ended CLK Drive
50Ω
4.7μF
0.1μF
1k
1k
NC7SVU04
FERRITE
BEAD
CLK
0.1μF
SUPPLY
CLEAN
LTC2228/
LTC2227/
LTC2226
222876 F11
The nature of the received signals also has a large bear-
ing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full scale, the use of these translators will have
a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass fi lter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for refl ections.
Figure 12. CLK Drive Using an LVDS or PECL-to-CMOS Converter
Figure 13. LVDS or PECL CLK Drive Using a Transformer
DIFFERENTIAL
CLOCK
INPUT
100Ω
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
4.7μF
ETC1-1T
5pF-30pF
FERRITE
BEAD
0.1μF
0.1μF
CLK
CLK
SUPPLY
FERRITE
CLEAN
BEAD
LTC2238/
LTC2237/
LTC2236
LTC2238/
LTC2237/
LTC2236
223876 F12
223876 F13
V
CM
222876fb