MG87FE/L2051 MEGAWIN [Megawin Technology Co., Ltd], MG87FE/L2051 Datasheet - Page 9

• Manufacturer Part Number: MG87FE/L2051
• Description: 8-bits microcontroll
• Manufacturer: MEGAWIN [Megawin Technology Co., Ltd]

5. 8051 CPU Function Description
5.1. CPU Register
PSW: Program Status Word
Address=D0H, read/write, Power On + RESET=0000-0000
CY: Carry bit.
AC: Auxiliary carry bit.
F0: General purpose flag 0.
RS1: Register bank select bit 1.
RS0: Register bank select bit 0.
OV: Overflow flag.
F1: General purpose flag 1.
P: Parity bit.
The program status word(PSW) contains several status bits that reflect the current state of the CPU. The PSW,
shown above, resides in the SFR space. It contains the Carry bit, the Auxiliary Carry(for BCD operation), the two
register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags.
The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the
“Accumulator” for a number of Boolean operations.
The bits RS0 and RS1 are used to select one of the four register banks shown in the on-chip-data-RAM section.
A number of instructions refer to these RAM locations as R0 through R7.
The Parity bit reflects the number of 1s in the Accumulator. P=1 if the Accumulator contains an odd number of 1s
and otherwise P=0.
SP: Stack Pointer
Address=81H, read/write, Power On + RESET=0000-0111
DPL: Data Pointer Low
Address=82H, read/write, Power On + RESET=0000-0000
DPH: Data Pointer High
Address=83H, read/write, Power On + RESET=0000-0000
B: B Register
Address=F0H, read/write, Power On + RESET=0000-0000
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
DPH[7]
DPL[7]
SP[7]
B[7]
CY
7
7
7
7
7
MEGAWIN
MAKE YOU WIN
DPH[6]
DPL[6]
SP[6]
B[6]
AC
6
6
6
6
6
DPH[5]
DPL[5]
SP[5]
B[5]
F0
5
5
5
5
5
DPH[4]
DPL[4]
SP[4]
RS1
B[4]
4
4
4
4
4
DPH[3]
DPL[3]
SP[3]
RS0
B[3]
3
3
3
3
3
DPH[2]
DPL[2]
SP[2]
B[2]
OV
2
2
2
2
2
MG87FE/L2051/4051/6051
DPH[1]
DPL[1]
SP[1]
B[1]
F1
1
1
1
1
1
Preliminary Ver 1.00
DPH[0]
DPL[0]
SP[0]
B[0]
P
0
0
0
0
0
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