MG87FE/L2051 MEGAWIN [Megawin Technology Co., Ltd], MG87FE/L2051 Datasheet - Page 22

• Manufacturer Part Number: MG87FE/L2051
• Description: 8-bits microcontroll
• Manufacturer: MEGAWIN [Megawin Technology Co., Ltd]

when the service routine is vectored to. The service routine should poll RI and TI to determine which one to
request service and it will be cleared by software.
/INT2 and Analog Comparator share the same interrupt vector, 33H. If IE.EAC is enabled, the interrupt vector,
33H will be used for Analog Comparator with the interrupt flag, ACSR.ACF, and IE2 will not be cleared when 33H
interrupt vector is addressed to.
If IE.EAC is disabled, the interrupt vector, 33H, will be used for /INT2 and the interrupt flag, XICON.IE2, that will
be cleared when EX2 is enabled and the interrupt vector is addressed to.
/INT3 and PWM-Timer share the same interrupt vector, 3BH. If CMOD.ECF is enabled, the interrupt vector, 3BH
will be used for PWM-Timer with the interrupt flag, CCON.CF, and IE3 will not be cleared when 3BH interrupt
vector is addressed to.
If CMOD.ECF is disabled, the interrupt vector, 3BH, will be used for /INT3 and the interrupt flag, XICON.IE3, that
will be cleared when EX3 is enabled and the interrupt vector is addressed to.
All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had
been set or cleared by hardware. In other words, interrupts can be generated or pending interrupts can be
canceled in software.
How hardware see the interrupts
Each interrupt flag is sampled at S5P2 of every machine cycle. The samples are polled during the next S5P2. If
one of the flags was in a set condition at S5P2 of the first cycle, the second cycle(polling cycle) will find it and the
interrupt system will generate an hardware LCALL to the appropriate service routine as long as it is not blocked
by any of the following conditions.
Block conditions:
Any of these three conditions will block the generation of the hardware LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine.
Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one or more
instruction will be executed before any interrupt is vectored to.
The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at
S5P2 of the previous machine cycle. Note that if an interrupt flag is active but not being responded to for one of
the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will
not be serviced. In other words, the interrupt flag was once active but not being responded to for one of the
above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not
be serviced. The interrupt flag was once active but not serviced is not kept in memory. Each polling cycle is new.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
22/56
An interrupt of equal or higher priority level is already in progress.
The current cycle (polling cycle) is not the final cycle in the execution of the instruction in progress.
The instruction in progress is RETI or any write to the IE, IP or IPH registers.
MEGAWIN
MAKE YOU WIN
MG87FE/L2051/4051/6051
Preliminary, v 1.03