AD5512AACPZ AD [Analog Devices], AD5512AACPZ Datasheet - Page 8

• Manufacturer Part Number: AD5512AACPZ
• Description: 2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDACs in LFCSP
• Manufacturer: AD [Analog Devices]

AD5541A/AD5542A/AD5512A
Table 5. AD5542A/AD5512A Pin Function Descriptions
10-Lead
LFCSP
8
6
2
3
5
4
7
9
Figure 10. AD5542A-1 10-Lead LFCSP Pin Configuration
Figure 11. AD5542 14-Lead SOIC Pin Configuration
14-Lead
SOIC
1
2
3
4
5
6
7
8
10
11
12
13
14
A G N D S
A G N D F
R E F S
R E F F
V
R F B
Pin No.
O U T
C S
16-Lead
TSSOP
1
2
3
4
5
6
8
9
11
10
12
13
14
16
15
N C = N O C O N N E C T
1
2
3
4
5
6
7
(N o t to S cale)
AD5542A
TO P V IE W
16-Lead
LFCSP
16
1
2
3
4
5
6
8
10
9
11
12
13
15
14
14
13
12
10
11
9
8
V
IN V
D G N D
L D A C
D IN
N C
S C L K
D D
Mnemonic
RFB
VOUT
AGNDF
AGNDS
REFS
REFF
CS
SCLK
CLR
DIN
LDAC
DGND
INV
VDD
VLOGIC
Rev. PrA | Page 8 of 24
Description
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op
amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V
reference. Reference can range from 2 V to V
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V
reference. Reference can range from 2 V to V
Logic Input Signal. The chip select signal is used to frame the serial data
input.
Clock Input. Data is clocked into the input register on the rising edge of SCLK.
Duty cycle must be between 40% and 60%.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR
is low, all LDAC pulses are ignored. When CLR is activated, the input register
and the DAC register are cleared to the model selectable midscale or
zeroscale .
Serial Data Input. This device accepts 16-bit words. Data is clocked into the
input register on the rising edge of SCLK.
LDAC Input. When this input is taken low, the DAC register is simultaneously
updated with the contents of the input register.
Digital Ground. Ground reference for digital circuitry.
Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin
to external op amps inverting input in bipolar mode.
Analog Supply Voltage, 5 V ± 10%.
Logic Power Supply.
N C = N O C O N N E C T
Figure 12. AD5542A 16-Lead TSSOP Pin Configuration
Figure 13. AD5542A 16-Lead LFCSP Pin Configuration
(N o t to S cale)
VOUT
AGNDF
AGNDS
REFS
RFB
VOUT
AGNDF
AGNDS
REFS
REFF
NC
CS
Preliminary Technical Data
1
4
2
3
1
2
3
4
5
6
7
8
N C = N O C O N N E C T
(N o t to S cale)
TO P V IE W
A D 5542A
AD5542A
AD5512A
DD
DD
V IE W
TO P
.
.
16
15
14
13
12
11
10
9
VDD
VLOGIC
INV
DGND
LDAC
CLR
DIN
SCLK
11
10
12
9
LDAC
CLR
DIN
DGND