AD5512AACPZ AD [Analog Devices], AD5512AACPZ Datasheet - Page 5

• Manufacturer Part Number: AD5512AACPZ
• Description: 2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDACs in LFCSP
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Parameter
POWER REQUIREMENTS
1
2
TIMING CHARACTERISTICS
V
unless otherwise noted.
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
1
2
3
4
5
6
7
8
9
9
10
11
12
13
Reference input resistance is code-dependent, minimum at 0x8555.
Guaranteed by design, not subject to production test.
Guaranteed by design and characterization. Not production tested
All input signals are specified with t
LOGIC
V
I
V
I
Power Dissipation
DD
LOGIC
DD
LOGIC
= 1.8 V to 5.5 V V, V
1, 2
Limit
50
20
10
10
5
7
15
10
7
5
5
15
15
15
15
DD
= 5V, V
R
= t
F
= 1 ns/V and timed from a voltage level of (V
REF
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
= 2.5 V, V
Min
2.7
1.8
INH
Typ
200
200
1.5
= 90% of V
Figure 5. Timing Diagram
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (V
Data hold time (V
LDAC pulsewidth
CS high to LDAC low setup
CS high time between active periods
CLR pulsewidth
Rev. PrA | Page 5 of 24
Max
5.5
TBD
5.5
TBD
TBD
LOGIC
, V
INL
INL
+ V
= 10% of V
INH
INH
INH
)/2.
Unit
V
µA
V
µA
mW
= 90% of V
= 3V, V
LOGIC
INL
= 0 V)
, AGND = DGND = 0 V;
AD5541A/AD5542A/AD5512AA
DD
, V
Test Condition
INL
= 10% of V
DD
)
−40°C < T
A
< +105°C,