LP3907SQ-JIXI INTERSIL [Intersil Corporation], LP3907SQ-JIXI Datasheet - Page 35

• Manufacturer Part Number: LP3907SQ-JIXI
• Description: Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface
• Manufacturer: INTERSIL [Intersil Corporation]

BUCK FUNCTION REGISTER (BFCR) – 0x38
This register allows the Buck switcher clock frequency to be
spread across a wider range, allowing for less Electro-mag-
This register also allows dynamic scaling of the nPOR Delay
Timing. The LP3907 is equipped with an internal Power-On-
Reset (“POR”) circuit which monitors the output voltage levels
on the buck regulators, allowing the user to more actively
monitor the power status of the chip.
The Under Voltage Lock-Out feature continuously monitor the
raw input supply voltage (VINLDO12) and automatically dis-
ables the four voltage regulators whenever this supply voltage
Name
Access
Data
Reset
Reserved
D7-2
000
—
—
BP_UVLO
R/W
Bypass UVLO
monitoring
0 - Allow UVLO
1 - Disable UVLO
D4
0
TPOR
R/w
nPOR Delay Timing
00 - 50µs
01 - 50ms
10 - 100ms
11 - 200ms
D3
01
35
netic Interference (EMI). The spread spectrum modulation
frequency refers to the rate at which the frequency ramps up
and down, centered at 2MHz.
is less than 2.8VDC. This prevents the user from damaging
the power source (i.e. battery), but can be disabled if the user
wishes.
Note that if the supply to VDD_M is close to 2.8V with a heavy
load current on the regulators, the chip is in danger of pow-
ering down due to UVLO. If the user wishes to keep the chip
active under those conditions, enable the “Bypass UVLO”
feature.
BK_SLOMOD
R/W
Buck Spread Spectrum
Modulation
0 – 10 kHz triangular wave
1 – 2 kHz triangular wave
D1
1
BK_SSEN
R/W
Spread Spectrum
Function Output
0 – Disabled
1 – Enabled
D0
0
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