LP3907SQ-JIXI INTERSIL [Intersil Corporation], LP3907SQ-JIXI Datasheet - Page 28

• Manufacturer Part Number: LP3907SQ-JIXI
• Description: Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface
• Manufacturer: INTERSIL [Intersil Corporation]

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TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledged related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying acknowledgement.
A receiver which has been addressed must generate an ac-
knowledgement (“ACK”) after each byte has been received.
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = LP3907 LLP chip address: 0x60; micro SMD chip address: 0x61
When a READ function is to be accomplished, a WRITE func-
tion must precede the READ function, as shown in the Read
Cycle waveform.
I
2
C Chip Address (see note above)
I
I
2
2
C Write Cycle
C Read Cycle
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After the START condition, the I
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). Please note that ac-
cording to industry I
of an 8-bit address is removed, and communication actually
starts with the 7th most significant bit. For the eighth bit (LSB),
a “0” indicates a WRITE and a “1” indicates a READ. The
second byte selects the register to which the data will be writ-
ten. The third byte contains data to write to the selected
register.
The LP3907 has factory-programmed I
LLP chip has a chip address of 60'h, while the micro SMD chip
has a chip address of 61'h.
2
C standards for 7-bit addresses, the MSB
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2
C master sends a chip ad-
2
C addresses. The
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