LP3907SQ-JIXI INTERSIL [Intersil Corporation], LP3907SQ-JIXI Datasheet - Page 30

• Manufacturer Part Number: LP3907SQ-JIXI
• Description: Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface
• Manufacturer: INTERSIL [Intersil Corporation]

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EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION
BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10
This register controls the enables for the Bucks and LDOs.
BUCK AND LDO STATUS REGISTER (BKLDOSR) – 0X11
This register monitors whether the Bucks and LDOs meet the voltage output specifications.
BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) – 0X20
This register selects and controls the output target voltages for the buck regulators.
Name
Access
Data
Reset
Name
Access
Data
Reset
Name
Access
Data
Reset
D7
BKS_OK
R
0 – Buck 1-2
Not Valid
1 – Bucks
Valid
0
D7-6
—
—
Reserved
00
D7
—
—
Reserved
0
EN_DLY<2:0>
000
001
010
011
100
101
110
111
D5
B2VS
R/W
Buck2 Target Voltage
Select
0 – B2VT1
1 – B2VT2
0
D6
LDO2EN
R/W
0 – Disable
1 – Enable
1
D6
LDOS_OK
R
0 – LDO 1-2
Not Valid
1 – LDOs Valid
0
D5
—
—
Reserved
1
D5
LDO2_OK
R
0 – LDO2 Not
Valid
1 – LDO2 Valid
0
D4
B2GO
R/W
Buck2 Voltage Ramp
CTRL
0 – Hold
1 – Ramp to B2VS
selection
0
Buck1
1.5
1.5
1.5
1.5
1
1
3
2
D4
LDO1EN
R/W
0 – Disable
1 – Enable
1
D4
LDO1_OK
R
0 – LDO1 Not
Valid
1 – LDO1 Valid
0
30
D3-2
—
—
Reserved
00
D3
—
—
Reserved
0
Buck2
D3
—
—
Reserve
d
0
1.5
1.5
1
2
2
2
2
3
Delay (ms)
D1
B1VS
R/W
Buck1 Target Voltage
Select
0 – B1VT1
1 – B1VT2
0
D2
BK2EN
R/W
0 – Disable
1 – Enable
1
D2
BK2_OK
R
0 – Buck2 Not
Valid
1 – Buck2
Valid
0
LDO1
1
2
3
1
3
2
1
6
D1
—
—
Reserved
0
D1
—
—
Reserve
d
0
D0
B1GO
R/W
Buck1 Voltage Ramp
CTRL
0 – Hold
1 – Ramp to B1VS
selection
0
D0
BK1_OK
R
0 – Buck1 Not
Valid
1 – Buck1
Valid
0
D0
BK1EN
R/W
0 – Disable
1 – Enable
1
LDO2
1.5
11
1
2
6
1
6
2