CY28435OXCT SPECTRALINEAR [SpectraLinear Inc], CY28435OXCT Datasheet - Page 7

• Manufacturer Part Number: CY28435OXCT
• Description: Clock Generator for Intel Grantsdale Chipset
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 20, 2006
Byte 5: Control Register 5 (continued)
Byte 6: Control Register 6
Byte 7: Vendor ID
Byte 8: Control Register 8
Bit
Bit
Bit
Bit
1
7
6
5
4
3
0
7
6
5
4
3
2
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
@Pup
HW
HW
HW
HW
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
PCI, PCIF and SRC clock
outputs except those set
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
CPU_DWN_SS
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
to free running
SRC_SS_OFF
TEST_MODE
RESERVED
TEST_SEL
CPU[T/C]0
CPU_SS
SRC_SS
Name
Name
Name
Name
FS_D
REF0
FS_C
FS_B
FS_A
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
FS_D reflects the value of the FS_D pin sampled on power-up.
0 = FS_D was LOW during VTT_PWRGD# assertion
REF Output Drive Strength
0 = High, 1 = Low
SW PCI_STP# Function
0 = SW PCI_STP# assert, 1= SW PCI_STP# deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
FS_C Reflects the value of the FS_C pin sampled on power-up
0 = FS_C was LOW during VTT_PWRGD# assertion
FS_B Reflects the value of the FS_B pin sampled on power-up
0 = FS_B was LOW during VTT_PWRGD# assertion
FS_A Reflects the value of the FS_A pin sampled on power-up
0 = FS_A was LOW during VTT_PWRGD# assertion
Spread Selection for CPU PLL
0: –0.5% (peak to peak)
1: –1.0% (peak to peak)
Spread Selection for CPU PLL
0: Down spread.
1: Center spread
SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Spread Selection for SRC PLL
0: –0.5% (peak to peak)
1: –1.0% (peak to peak)
RESERVED, Set = 0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Description
Description
Description
CY28435
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