CY28435OXCT SPECTRALINEAR [SpectraLinear Inc], CY28435OXCT Datasheet - Page 12

• Manufacturer Part Number: CY28435OXCT
• Description: Clock Generator for Intel Grantsdale Chipset
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 20, 2006
Dynamic Frequency
Dynamic Frequency – Dynamic Frequency (DF) is a technique
to increase the CPU frequency dynamically from any starting
value. The user selects the starting point, either by HW, FSEL,
or DAF then enables DF. After that, DF will dynamically change
as determined by the value on the DF[2:0] pins.
DF/PCI pin – These PCI pins incorporate dual functions, either
DF or PCI. The function is selected by the DF_EN pin. When
used as DF, these three pins will map to eight entries that
correspond to different “N” values for Dynamic Frequency.
Below is a table that lists the combinations along with the
increase in “N”.
DF_EN bit – This bit enables the DF mode. By default, it is not
set. When set, the operating frequency is determined by
DF[2:0] pins. Default = 0, (No DF)
DF_Limit bit – There are three bits that allow the user to set an
upper limit to prevent CPU runaway. In the event that the user
uses DAF with DF, this feature will provide some safeguard so
the CPU won’t burn up.
Dial-A-Frequency (CPU & SRC)
This feature allows the user to overclock their system by slowly
stepping up the CPU or SRC frequency. When the program-
mable output frequency feature is enabled, the CPU and SRC
frequencies are determined by the following equation:
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively. “G” stands for the PLL Gear Constant, which is
determined by the programmed value of FS[E:A]. See
Figure 1 for the Gear Constant for each Frequency selection.
The PCI Express only allows user control of the N register, the
M value is fixed and documented in Figure 1.
In this mode, the user writes the desired N and M value into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value if required.
Associated Register Bits
CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note: the CPU_DAF_N and M register must contain
valid values before CPU_DAF is set. Default = 0 (No DAF).
DOC[2:0]
000
001
010
100
101
011
110
111
Original Frequency
DOC N value
+10
+14
+18
+30
+40
+2
+6
CPU_DAF_N – There are 9 bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
frequency select table in Figure 1.
CPU_DAF_M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, the allowable values for M are detailed in the frequency
select table in section Figure 1.
SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note: the SRC_DAF_N register must contain valid
values before SRC_DAF is set. Default = 0 (No DAF).
SRC_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0 (0000). The allowable values for N are detailed in the
frequency select table in Figure 1.
Recovery – The recovery mechanism during CPU DAF when
the system locks up and the watchdog timer is enabled is
determined by the “Watchdog Recovery Mode” and
“Watchdog Auto recovery Enable” bits. The possible recovery
methods are: (A) Auto, (B) Manual (by Recovery N), (C) HW,
and (D) No recovery—just send reset signal.
There is no recovery mode for SRC Dial-a-frequency.
Software Frequency Select
This mode allows the user to select the CPU output
frequencies using the Software Frequency select bits in the
SMBUS register.
FSEL – There are 4 bits (for 16 combinations) to select prede-
termined CPU frequencies from a table. The table selections
are detailed in section Figure 1
FS_Override – This bit allows the CPU frequency to be
selected from HW or FSEL settings. By default, this bit is not
set and the CPU frequency is selected by HW. When this bit
is set, the CPU frequency is selected by the FSEL bits. Default
= 0.
Recovery – The recovery mechanism during FSEL when the
system locks up is determined by the “Watchdog Recovery
Mode” and “Watchdog Auto recovery Enable” bits. The only
possible recovery method is from the Hardware Settings. Auto
recovery or manual recovery can cause a wrong output
frequency because the output divider may have changed with
the selected CPU frequency and these recovery methods will
not recover the original output divider setting.
Smooth Switching
The device contains one smooth switch circuit that is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667
overshoot and undershoot will be less than 2%.
The Smooth Switch circuit can be assigned to either PLL via
register byte 14 bit 4. By default the smooth switch circuit is
assigned to the CPU PLL. Either PLL can still be overclocked
when it does not have control of the smooth switch circuit but
s. The frequency
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