CY28411OCT SPECTRALINEAR [SpectraLinear Inc], CY28411OCT Datasheet
CY28411OCT
Related parts for CY28411OCT
CY28411OCT Summary of contents
Page 1
Features • Compliant to Intel CK410M • Supports Intel Pentium-M CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100 MHz differential SRC clocks • 96 MHz differential dot clock • 48 MHz USB clocks Block Diagram XIN ...
Page 2
Pin Definitions Pin No. Name 54 CPU_STP# 44,43,41,40 CPUT/C 36,35 CPUT2_ITP/SRCT7, CPUC2_ITP/SRCC7 14,15 DOT96T, DOT96C 12 FS_A/USB_48 16 FS_B/TEST_MODE 53 FS_C/TEST_SEL 39 IREF 56,3,4,5 PCI 55 PCI_STP# 8 PCIF0/ITP_EN 9 PCIF1 52 REF 46 SCLK 47 SDATA 26,27 SRC4_SATAT, SRC4_SATAC ...
Page 3
Frequency Select Pins (FS_A, FS_B and FS_C) Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by ...
Page 4
Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description 28 Acknowledge from slave 36:29 Data byte 1 – 8 bits 37 Acknowledge from slave 45:38 Data byte 2 – 8 bits 46 Acknowledge from slave ...
Page 5
Byte 0:Control Register 0 (continued) Bit @Pup Byte 1: Control Register 1 Bit @Pup DOT_96T Byte 2: Control ...
Page 6
Byte 3: Control Register 3 (continued) Bit @Pup Byte 4: Control Register 4 Bit @Pup ...
Page 7
Byte 6: Control Register 6 Bit @Pup PCIF, SRC, PCI 2 Externally selected 1 Externally selected 0 Externally selected Byte 7: Vendor ID Bit @Pup 7 0 Revision Code Bit ...
Page 8
Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with ...
Page 9
PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an ...
Page 10
CPU_STP# Assertion The CPU_STP# signal is an active low input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that ...
Page 11
CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 8. CPU_STP# = Hi-Z, CPU_PD = Hi-Z, DOT_PD = tHi-Z [1] PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI ...
Page 12
FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM VDD Clock Gen Clock State State 0 Off Clock Outputs Off Clock VCO VDD_A = 2.0V S0 Power Off Figure 12. Clock Generator Power-up/Run State Diagram Rev 1.0, November 22, 2006 0.2-0.3mS W ait ...
Page 13
Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC (Mil-Spec 883E ...
Page 14
AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU at 0.7V T ...
Page 15
AC Electrical Specifications Parameter Description T SRCT/C Cycle to Cycle Jitter CCJ L SRCT/C Long Term Accuracy ACC SRCT and SRCC Rise and Fall Times Rise/Fall Matching RFM T Rise TimeVariation R T Fall ...
Page 16
AC Electrical Specifications Parameter Description T Period PERIOD T Absolute Period PERIODAbs T USB high time HIGH T USB low time LOW Rise and Fall Times Cycle to Cycle Jitter CCJ REF T REF ...
Page 17
... Figure 15. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Standard CY28411OC 56-pin SSOP CY28411OCT 56-pin SSOP – Tape and Reel CY28411ZC 56-pin TSSOP CY28411ZCT 56-pin TSSOP – Tape and Reel Lead-free CY28411OXC 56-pin SSOP CY28411OXCT 56-pin SSOP – ...
Page 18
Package Drawing and Dimensions 28 29 0.088 0.092 0.025 BSC 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 0.249[0.009 13.894[0.547] 14.097[0.555] 0.851[0.033] 0.500[0.020] 0.950[0.037] BSC While SLI has reviewed all information herein ...