CY28405OC-2 SPECTRALINEAR [SpectraLinear Inc], CY28405OC-2 Datasheet - Page 35

• Manufacturer Part Number: CY28405OC-2
• Description: Clock Synthesizer with Differential SRC and CPU Outputs
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 22, 2006
Table 1. Frequency Select Table (FS_A FS_B)
Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
izes to their default setting upon power-up, and therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for pow-
er management functions.
Table 3. Command Code Definition
Table 4. Block Read and Block Write Protocol
FS_A
FS_A
20:27
29:36
38:45
11:18
0
0
0
1
1
0
0
1
(6:0)
2:8
Bit
Bit
10
19
28
37
46
....
1
9
7
FS_B
FS_B
B6b7
B6b7
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 Bit
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
0
1
0
0
1
0
Block Write Protocol
100 MHz
200 MHz
133 MHz
200 MHz
400 MHz
266 MHz
REF/N
CPU
CPU
Hi-Z
Description
100/200 MHz
100/200 MHz
100/200 MHz
100/200 MHz
100/200 MHz
100/200 MHz
REF/N
SRC
SRC
Hi-Z
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
REF/N
3V66
3V66
Hi-Z
Description
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
39:46
11:18
21:27
30:37
PCIF/PCI
PCIF/PCI
Bit
2:8
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
10
19
20
28
29
38
REF/N
1
9
Hi-Z
Data byte from slave – 8 bits
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 Bit
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge from master
14.3 MHz
14.3 MHz
14.3 MHz
14.3 MHz
14.3 MHz
14.3 MHz
Block Read Protocol
REF/N
REF0
REF0
Hi-Z
Description
14.31 MHz
14.31 MHz
14.31 MHz
14.31 MHz
14.31 MHz
14.31 MHz
REF/N
REF1
REF1
Hi-Z
CY28405-2
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USB/DOT
USB/DOT
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
REF/N
Hi-Z