PLL520-28 PhaseLink (PLL), PLL520-28 Datasheet - Page 4

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PLL520-28

Manufacturer Part Number
PLL520-28
Description
, 120-200MHz In, 120-200MHz Out, Pecl
Manufacturer
PhaseLink (PLL)
Datasheet
4. General Electrical Specifications
5. Jitter specifications
*: To be measured
6. Phase noise specifications
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Supply Current (Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-peak
Integrated jitter RMS at 155MHz
Phase Noise relative to
carrier
PARAMETERS
PARAMETERS
PARAMETERS
155.52MHz
FREQUENCY
Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
SYMBOL
V
I
DD
DD
At 155.52MHz, with capacitive decoupling
between VDD and GND.
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles.
Integrated 12 kHz to 20 MHz
PECL/LVDS/CMOS
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
@10Hz
-75
CONDITIONS
CONDITIONS
@100Hz
-95
Preliminary
@1kHz
-125
PLL520-28/-29
MIN.
MIN.
3.13
45
45
Universal Low Phase Noise IC’s
@10kHz
-140
TYP.
TYP.
45*
0.3
25
50
50
7*
4
50
@100kHz
Rev 10/29/02 Page 4
100/80/40
-145
MAX.
MAX.
3.47
55
55
UNITS
dBc/Hz
UNITS
UNITS
mA
mA
ps
ps
ps
%
V

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