PLL520-00D1 PhaseLink (PLL), PLL520-00D1 Datasheet

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PLL520-00D1

Manufacturer Part Number
PLL520-00D1
Description
, Low Phase Noise Vcxo With Multipliers
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTIONS
PLL520-00 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its design
was optimized to tolerate higher limits of
interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. Its internal varicaps allow an on chip
frequency pulling, controlled by the VCON input.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
VCON
SEL
X+
X-
120MHz to 200MHz Fundamental Mode Crystal.
Output range: 120 – 200MHz (no multiplication),
240 – 400MHz (2x multiplier) or 480 – 700MHz
(4x multiplier).
Available outputs: PECL, LVDS, or CMOS.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
Low Phase Noise VCXO with multipliers (for 120-200MHz Fund Xtal)
integrated
Oscillator
Amplifier
varicaps
w/
PLL by-pass
Locked
(Phase
Loop)
PLL
PLL520-00
OE
Q
Q
DIE CONFIGURATION
DIE SPECIFICATIONS
OUTPUT SELECTION AND ENABLE
Pad #9, 18, 25: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through internal pull-up/-down.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1”
Y
OE_SELECT
X
1 (Default)
OUTSEL1
(Pad #9)
Pad #18
Pad dimensions
(0,0)
Reverse side
Logical states defined by CMOS levels if OE_SELECT is “0”
Thickness
0
0
1
1
0
Name
26
27
28
29
30
31
Size
Preliminary
25
1
24
2
23
1 (Default)
0 (Default)
OE_CTRL
(Pad #30)
3
OUTSEL0
Pad #25
22
4
0
1
21
0
1
0
1
PLL520-00D1
65 mil
5
20
6
80 micron x 80 micron
Tri-state
Output enabled
Output enabled
Tri-state
19
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
7
62 x 65 mil
Selected Output
18
8
Value
10 mil
GND
State
Rev 06/26/03 Page 1
12
11
10
17
16
15
14
13
9
(1550,1475)

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PLL520-00D1 Summary of contents

Page 1

... Pad #9, 18, 25: Bond to GND to set to “0”, bond to VDD to set to “1” No connection results to “default” setting through internal pull-up/-down. Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1” Logical states defined by CMOS levels if OE_SELECT is “0” PLL520-00D1 Preliminary 65 mil (1550,1475) ...

Page 2

... Fin Fin multiplication (no PLL) SYMBOL SYMBOL CONDITIONS F Parallel Fundamental Mode XIN C Die at VCON = 1.65V L (xtal cut (xtal cut E PLL520-00D1 Preliminary Selected Multiplier MIN. MAX -0 -0 -65 150 ...

Page 3

... From power valid VCXOSTB XTAL C /C < 300 VCON 3.3V at room temperature VCON = 0 to 3.3V 0V VCON 3.3V, -3dB SYMBOL CONDITIONS I PECL/LVDS/CMOS 1.4V (CMOS) @ 1.25V (LVDS) @ Vdd – 1.3V (PECL) PLL520-00D1 Preliminary MIN. TYP. MAX. 10 200* 100* 4 – 18 MIN. TYP. MAX. 100/80/40 3.13 3. ...

Page 4

... At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz @10Hz @100Hz -75 -95 -75 -95 PLL520-00D1 Preliminary MIN. TYP. MAX. 2.5 18 2.5 ...

Page 5

... -4mA (Standard drive) OHC OH At TTL level (High drive) At TTL level (Standard drive) SYMBOL CONDITIONS 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load PLL520-00D1 Preliminary MIN. TYP. MAX. 2.4 0.4 V – 0 MIN. TYP. ...

Page 6

... I OSD SYMBOL CONDITIONS R = 100 (see figure LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80 DIFF 20 PLL520-00D1 Preliminary MIN. TYP. MAX. 247 355 454 -50 50 1.4 1.6 0.9 1.1 1.125 1.2 1.375 -5.7 -8 MIN. TYP. MAX. 0.2 0.7 1.0 0.2 0.7 1.0 LVDS Switching Test Circuit ...

Page 7

... V OL SYMBOL CONDITIONS @20/80% - PECL t r @80/20% - PECL t f PECL Output Skew VDD OUT 2.0V 50% OUT PECL Transistion Time Waveform DUTY CYCLE PLL520-00D1 Preliminary MIN. MAX. V – 1.025 DD V – 1.620 DD MIN. TYP. MAX. 0.6 1.5 0.5 1.5 t SKEW Rev 06/26/03 Page 7 UNITS V V UNITS ...

Page 8

... PLL520-00D1 Rev 06/26/03 Page 8 ...

Page 9

... President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Preliminary PART NUMBER PLL520-00 DC – D1 REVISION TEMPERATURE C=COMMERCIAL PACKAGE TYPE D=DIE Marking Package Option PLL520-00DC-D1 Die – Waffle Pack PLL520-00D1 Rev 06/26/03 Page 9 ...

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